AM79C970A datasheet(122/219 Pages) AMD

122 / 219 page

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P R E L I M I N A R Y

122

Am79C970A

Read/Write accessible always.

MPEN is cleared to ZERO by

H_RESET or S_RESET and is

not

affected

setting

the

STOP bit.

MPMODE

Magic Packet Mode. Setting

MPMODE to ONE will redefine

the

SLEEP pin to be a magic

packet

enable

pin.

The

PCnet-PCI II controller will enter

the magic packet mode when

MPMODE is set to one and either

SLEEP is asserted or MPEN is

set to ONE.

Read/Write accessible always.

MPMODE is cleared to ZERO by

H_RESET or S_RESET and is

not

affected

setting

the

STOP bit.

SPND

Suspend. Setting SPND to ONE

will cause the PCnet-PCI II con-

troller to start entering the sus-

pend mode. The host must poll

SPND until it reads back ONE to

determine that the PCnet-PCI II

controller has entered the sus-

pend mode. Setting SPND to

ZERO will get the PCnet-PCI II

controller out of suspend mode.

SPND can only be set to ONE if

STOP (CSR0, bit 2) is cleared to

ZERO. H_RESET, S_RESET or

setting the STOP bit will get the

PCnet-PCI II controller out of

suspend mode.

When the host requests the

PCnet-PCI II controller to enter

the suspend mode, the device

first finishes all on-going transmit

activity and updates the corre-

sponding transmit descriptor en-

tries. It then finishes all on-going

receive activity and updates the

corresponding receive descriptor

entries. It then sets the read-ver-

sion of SPND to ONE and enters

the suspend mode.

In suspend mode, all of the

CSR and BCR registers are

accessible.

long

the

PCnet-PCI II controller is not re-

set while in suspend mode (by

H_RESET, S_RESET or by set-

ting the STOP bit), no re-initiali-

zation of the device is required

after the device comes out of

suspend mode. The PCnet-PCI II

controller will continue at the

transmit and receive descriptor

ring locations where it had left off.

Read/Write accessible always.

SPND is cleared by H_RESET,

S_RESET or by setting the

STOP bit.

CSR6: RX/TX Descriptor Table Length

Bit

Name

Description

31–16

RES

Reserved locations. Written as

ZEROs and read as undefined.

15–12 TLEN

Contains a copy of the transmit

encoded ring length (TLEN) field

read from the initialization block

during PCnet-PCI II controller in-

itialization. This field is written

during the PCnet-PCI II controller

initialization routine.

Read

accessible

only

when

either the STOP or the SPND bit

is set. Write operations have no

effect and should not be per-

formed. TLEN is only defined

after initialization. These bits

are unaffected by H_RESET,

S_RESET or by setting the

STOP bit.

11–8

RLEN

Contains a copy of the receive

encoded ring length (RLEN) read

from

the

initialization

block

during PCnet-PCI II controller

initialization. This field is written

during the PCnet-PCI II controller

initialization routine.

Read

accessible

only

when

either the STOP or the SPND bit

is set. Write operations have no

effect and should not be per-

formed. RLEN is only defined af-

ter

initialization.

These

bits

are unaffected by H_RESET,

S_RESET or by setting the

STOP bit.

7–0

RES

Reserved

locations.

Read

as ZEROs. Write operations

are ignored.

CSR8: Logical Address Filter 0

Bit

Name

Description

31–16

RES

Reserved locations. Written as

ZEROs and read as undefined.

15–0LADRF[15:0]

Logical

Address

Filter,

LADRF[15:0]. The content of this

from the initialization block after

the INIT bit in CSR0 has been set

or a direct register write has been

performed on this register.

Read/Write

accessible

only

when either the STOP or the

SPND bit is set. These bits

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