AM79C970A datasheet(123/219 Pages) AMD

123 / 219 page

P R E L I M I N A R Y

AMD

123

Am79C970A

are unaffected by H_RESET,

S_RESET or by setting the

STOP bit.

CSR9: Logical Address Filter 1

Bit

Name

Description

31–16

RES

Reserved locations. Written as

ZEROs and read as undefined.

15–0LADRF[31:16]

Logical

Address

Filter,

LADRF[31:16]. The content of

this register is undefined until

loaded from the initialization

block after the INIT bit in CSR0

has been set or a direct register

write has been performed on

this register.

Read/Write

accessible

only

when either the STOP or the

SPND bit is set. These bits

are unaffected by H_RESET,

S_RESET or by setting the

STOP bit.

CSR10: Logical Address Filter 2

Bit

Name

Description

31–16

RES

Reserved locations. Written as

ZEROs and read as undefined.

15–0LADRF[47:32]

Logical

Address

Filter,

LADRF[47:32]. The content of

this register is undefined until

loaded from the initialization

block after the INIT bit in CSR0

has been set or a direct register

write has been performed on

this register.

Read/Write

accessible

only

when either the STOP or the

SPND bit is set. These bits

are unaffected by H_RESET,

S_RESET or by setting the

STOP bit.

CSR11: Logical Address Filter 3

Bit

Name

Description

31–16

RES

Reserved locations. Written as

ZEROs and read as undefined.

15–0LADRF[63:48]

Logical

Address

Filter,

LADRF[63:48]. The content of

this register is undefined until

loaded from the initialization

block after the INIT bit in CSR0

has been set or a direct register

write has been performed on

this register.

Read/Write

accessible

only

when either the STOP or the

SPND bit is set. These bits

are unaffected by H_RESET,

S_RESET or by setting the

STOP bit.

CSR12: Physical Address Register 0

Bit

Name

Description

31–16

RES

Reserved locations. Written as

ZEROs and read as undefined.

15–0PADR[15:0]

Physical

Address

PADR[15:0]. The content of this

from the initialization block after

the INIT bit in CSR0 has been set

or a direct register write has been

performed on this register.

Read/Write

accessible

only

when either the STOP or the

SPND bit is set. These bits

are unaffected by H_RESET,

S_RESET or by setting the

STOP bit.

CSR13: Physical Address Register 1

Bit

Name

Description

31–16

RES

Reserved locations. Written as

ZEROs and read as undefined.

15–0PADR[31:16]

Physical

Address

PADR[31:16]. The content of this

from the initialization block after

the INIT bit in CSR0 has been set

or a direct register write has been

performed on this register.

Read/Write

accessible

only

when either the STOP or the

SPND bit is set. These bits

are unaffected by H_RESET,

S_RESET or by setting the

STOP bit.

CSR14: Physical Address Register 2

Bit

Name

Description

31–16

RES

Reserved locations. Written as

ZEROs and read as undefined.

15–0PADR[47:32]

Physical

Address

PADR[47:32]. The content of this

from the initialization block after

the INIT bit in CSR0 has been set

or a direct register write has been

performed on this register.

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