AM79C970A datasheet(129/219 Pages) AMD

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AMD

129

Am79C970A

CSR33: Next Transmit Descriptor Address Upper

Bit

Name

Description

31–16

RES

Reserved locations. Written as

ZEROs and read as undefined.

15–0 NXDAU

Contains the upper 16 bits of

the

transmit

descriptor

address pointer.

Read/Write

accessible

only

when either the STOP or the

SPND bit is set. These bits

are unaffected by H_RESET,

S_RESET or by setting the

STOP bit.

CSR34: Current Transmit Descriptor Address

Lower

Bit

Name

Description

31–16

RES

Reserved locations. Written as

ZEROs and read as undefined.

15–0

CXDAL

Contains the lower 16 bits of the

current

transmit

descriptor

address pointer.

Read/Write

accessible

only

when either the STOP or the

SPND bit is set. These bits

are unaffected by H_RESET,

S_RESET or by setting the

STOP bit.

CSR35: Current Transmit Descriptor Address

Upper

Bit

Name

Description

31–16

RES

Reserved locations. Written as

ZEROs and read as undefined.

15–0 CXDAU

Contains the upper 16 bits of the

current transmit descriptor ad-

dress pointer.

Read/Write

accessible

only

when either the STOP or the

SPND bit is set. These bits

are unaffected by H_RESET,

S_RESET or by setting the

STOP bit.

CSR36: Next Next Receive Descriptor Address

Lower

Bit

Name

Description

31–16

RES

Reserved locations. Written as

ZEROs and read as undefined.

15–0 NNRDAL

Contains the lower 16 bits of the

receive

descriptor

address pointer.

Read/Write

accessible

only

when either the STOP or the

SPND bit is set. These bits

are unaffected by H_RESET,

S_RESET or by setting the

STOP bit.

CSR37: Next Next Receive Descriptor Address

Upper

Bit

Name

Description

31–16

RES

Reserved locations. Written as

ZEROs and read as undefined.

15–0 NNRDAU

Contains the upper 16 bits of the

receive

descriptor

address pointer.

Read/Write

accessible

only

when either the STOP or the

SPND bit is set. These bits

are unaffected by H_RESET,

S_RESET or by setting the

STOP bit.

CSR38: Next Next Transmit Descriptor Address

Lower

Bit

Name

Description

31–16

RES

Reserved locations. Written as

ZEROs and read as undefined.

15–0 NNXDAL

Contains the lower 16 bits of the

next next transmit descriptor

address pointer.

Read/Write

accessible

only

when either the STOP or the

SPND bit is set. These bits

are unaffected by H_RESET,

S_RESET or by setting the

STOP bit.

CSR39: Next Next Transmit Descriptor Address

Upper

Bit

Name

Description

31–16

RES

Reserved locations. Written as

ZEROs and read as undefined.

15–0 NNXDAU

Contains the upper 16 bits of the

next next transmit descriptor

address pointer.

Read/Write

accessible

only

when either the STOP or the

SPND bit is set. These bits

are unaffected by H_RESET,

S_RESET or by setting the

STOP bit.

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