AM79C970A datasheet(124/219 Pages) AMD

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P R E L I M I N A R Y

124

Am79C970A

Read/Write

accessible

only

when either the STOP or the

SPND bit is set. These bits

are unaffected by H_RESET,

S_RESET or by setting the

STOP bit.

CSR15: Mode

Bit

Name

Description

This register’s fields are loaded

during the PCnet-PCI II controller

initialization routine with the cor-

responding initialization block

values. The host can also write

directly to this register.

31–16

RES

Reserved locations. Written as

ZEROs and read as undefined.

PROM

Promiscuous Mode.

When PROM is set to ONE,

all

incoming

receive

frames

are accepted.

Read/Write

accessible

only

when either the STOP or the

SPND bit is set.

DRCVBC

Disable

Receive

Broadcast.

When

set,

this

bit

disables

the PCnet-PCI II controller from

receiving broadcast messages.

DRCVBC has no effect when

PROM is set to ONE.

Read/Write

accessible

only

when either the STOP or the

SPND bit is set. DRCVBC is

cleared

H_RESET

S_RESET

and

not

affected

by STOP.

DRCVPA

Disable Receive Physical Ad-

dress. When set, the physical ad-

dress detection (Station or node

ID) of the PCnet-PCI II controller

will be disabled. Frames ad-

dressed to the node’s individual

physical address will not be rec-

ognized. DRCVPA has no effect

when PROM is set to ONE.

Read/Write

accessible

only

when either the STOP or the

SPND bit is set.

DLNKTST

Disable

Link

Status.

When

DLNKTST is set to ONE, moni-

toring of Link Pulses is disabled.

When DLNKTST is cleared to

ZERO, monitoring of Link Pulses

is enabled. This bit only has

meaning when the 10BASE-T

network interface is selected.

Read/Write

accessible

only

when either the STOP or the

SPND bit is set.

DAPC

Disable Automatic Polarity Cor-

rection. When DAPC is set to

ONE, the 10BASE-T receive po-

larity reversal algorithm is dis-

abled. When DAPC is cleared to

ZERO, the polarity reversal algo-

rithm is enabled.

This bit only has meaning when

the 10BASE-T network interface

is selected.

Read/Write

accessible

only

when either the STOP or the

SPND bit is set.

MENDECL

MENDEC Loopback Mode. See

the description of the LOOP bit

in CSR15.

Read/Write

accessible

only

when either the STOP or the

SPND bit is set.

LRT

Low Receive Threshold (T-MAU

Mode only)

TSEL

Transmit

Mode

Select

(AUI

Mode only)

LRT

Low Receive Threshold. When

LRT is set to ONE, the internal

twisted pair receive thresholds

are reduced by 4.5 dB below

the standard 10BASE-T value

(approximately

3/5)

and

the

unsquelch

threshold

for

the

RXD circuit will be 180 mV–

312 mV peak.

Table 23. Network Port Configuration

ASEL

Link Status

PORTSEL[1:0]

(BCR2[1])

(of 10BASE-T)

Network Port

Fail

AUI

Pass

10BASE-T

AUI

10BASE-T

GPSI

Reserved

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