AM79C970A datasheet(126/219 Pages) AMD

126 / 219 page

AMD

P R E L I M I N A R Y

126

Am79C970A

Read/Write

accessible

only

when either the STOP or the

SPND bit is set.

DXMTFCS

Disable Transmit CRC (FCS).

When DXMTFCS is cleared to

ZERO,

the

transmitter

will

generate and append an FCS to

the transmitted frame. When

DXMTFCS is set to ONE, no FCS

is generated or sent with the

transmitted frame. DXMTFCS is

overridden when ADD_FCS is

set in TMD1.

DXMTFCS

set

and

ADD_FCS is clear for a particular

frame, no FCS will be generated.

The value of ADD_FCS is valid

only when STP is set in TMD1. If

ADD_FCS is set for a particular

frame, the state of DXMTFCS is

ignored and a FCS will be ap-

pended on that frame by the

transmit circuitry. See also the

ADD_FCS bit in TMD1.

This bit is called DTCR in the

C-LANCE (Am79C90).

Read/Write

accessible

only

when either the STOP or the

SPND bit is set.

LOOP

Loopback

Enable

allows

PCnet-PCI II controller to oper-

ate in full-duplex mode for test

purposes. The setting of the

full-duplex control bits in BCR9

have no effect when the device

operates

loopback

mode.

When LOOP is set to ONE,

loopback is enabled. In combina-

tion with INTL and MENDECL,

various loopback modes are

defined

the

Loopback

Configuration table.

Read/Write

accessible

only

when either the STOP or the

SPND bit is set. LOOP is cleared

by H_RESET or S_RESET and is

unaffected

setting

the

STOP bit.

DTX

Disable Transmit. When DTX is

set to ONE, the PCnet-PCI II con-

troller will not access the transmit

descriptor ring and therefore no

transmissions

are

attempted.

When DTX is cleared to ZERO,

TXON (CSR0, bit 4) is set to ONE

after STRT (CSR0, bit 1) has

been set to ONE.

Read/Write

accessible

only

when either the STOP or the

SPND bit is set.

DRX

Disable Receiver. When DRX is

set to ONE, the PCnet-PCI II con-

troller will not access the receive

descriptor ring and therefore all

receive frame data are ignored.

When DRX is cleared to ZERO,

RXON (CSR0, bit 5) is set to

ONE after STRT (CSR0, bit 1)

has been set to ONE.

Read/Write

accessible

only

when either the STOP or the

SPND bit is set.

CSR16: Initialization Block Address Lower

Bit

Name

Description

31–16

RES

Reserved locations. Written as

ZEROs and read as undefined.

15–0

IADRL

This register is an alias of CSR1.

Read/Write

accessible

only

when either the STOP or the

SPND bit is set.

CSR17: Initialization Block Address Upper

Bit

Name

Description

31–16

RES

Reserved locations. Written as

ZEROs and read as undefined.

15–0

IADRH

This register is an alias of CSR2.

Read/Write

accessible

only

when either the STOP or the

SPND bit is set.

CSR18: Current Receive Buffer Address Lower

Bit

Name

Description

31–16

RES

Reserved locations. Written as

ZEROs and read as undefined.

15–0

CRBAL

Contains the lower 16 bits of the

current receive buffer address at

which the PCnet-PCI II controller

will store incoming frame data.

Read/Write

accessible

only

when either the STOP or the

SPND bit is set. These bits

are unaffected by H_RESET,

S_RESET or by setting the

STOP bit.

CSR19: Current Receive Buffer Address Upper

Bit

Name

Description

31–16

RES

Reserved locations. Written as

ZEROs and read as undefined.

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