AM79C970A datasheet(120/219 Pages) AMD

120 / 219 page

AMD

P R E L I M I N A R Y

120

Am79C970A

Read/Write accessible always.

TXSTRTM is set to ONE by

H_RESET or S_RESET and is

unaffected

setting

the

STOP bit.

JAB

Jabber Error is set by the PCnet-

PCI II controller when the T-MAU

exceeds the allowed transmis-

sion time limit. Jabber can only

be asserted in 10BASE-T mode.

When JAB is set,

INTA is as-

serted if IENA is ONE and the

mask bit JABM is ZERO.

Read/Write accessible always.

JAB is cleared by the host by writ-

ing a ONE. Writing a ZERO has

no effect. JAB is cleared by

H_RESET, S_RESET or by set-

ting the STOP bit.

When the value 01h has been

programmed into the SWSTYLE

ILACC (Am79C900) compatibil-

ity, then this bit has no meaning

and PCnet-PCI II controller will

never set the value of this bit

to ONE.

JABM

Jabber Error Mask. If JABM is

set, the JAB bit will be masked

and unable to set the INTR bit.

Read/Write accessible always.

JABM

set

ONE

H_RESET or S_RESET and

is unaffected by setting the

STOP bit.

When the value 01h has been

programmed into the SWSTYLE

ILACC (Am79C900) compatibil-

ity, then this bit has no meaning

and PCnet-PCI II controller will

clear

the

value

this

bit

to ZERO.

CSR5: Extended Control and Interrupt

Bit

Name

Description

Certain bits in CSR5 indicate the

cause of an interrupt. The regis-

ter is designed so that these indi-

cator bits are cleared by writing

ONEs to those bit locations. This

means that the software can read

CSR5

and

write

back

the

value just read to clear the

interrupt condition.

31–16

RES

Reserved locations. Written as

ZEROs and read as undefined.

TOKINTD

Transmit OK Interrupt Disable. If

TOKINTD is set to ONE, the

TINT bit in CSR0 will not be set

when a transmission was suc-

cessful. Only a transmit error will

set the TINT bit.

TOKINTD has no effect when

LTINTEN (CSR5, bit 14) is set to

ONE. A transmit descriptor with

LTINT set to ONE will always

cause TINT to be set to ONE, in-

dependent of the success of

the transmission.

Read/Write accessible always.

TOKINTD

cleared

H_RESET or S_RESET and

is unaffected by setting the

STOP bit.

LTINTEN

Last Transmit Interrupt Enable.

When set to ONE, the LTINTEN

bit will cause the PCnet-PCI II

controller to read bit 28 of TMD1

as LTINT. The setting LTINT will

determine if TINT will be set at

the end of the transmission.

Read/Write accessible always.

LTINTEN

cleared

H_RESET or S_RESET and

is unaffected by setting the

STOP bit.

13–12

RES

Reserved locations. Written as

ZEROs and read as undefined.

SINT

System Interrupt is set by the

PCnet-PCI II controller when it

detects a system error during a

bus master transfer on the PCI

bus. System errors are data par-

ity error, master abort or a target

abort. The setting of SINT due to

a data parity error is not depend-

ent on the setting of PERREN

(PCI Command register, bit 6).

When SINT is set,

INTA is as-

serted if the enable bit SINTE is

ONE. Note that the assertion of

an interrupt due to SINT is not de-

pendent on the state of the INEA

bit, since INEA is cleared by the

STOP reset generated by the

system error.

Read/Write accessible always.

SINT is cleared by the host by

writing a ONE. Writing a ZERO

has no effect. The state of SINT

is not affected by clearing any of

the PCI Status register bits that

get set when a data parity error

(DATAPERR, bit 8), master abort

(RMABORT, bit 13) or target

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