AM79C970A datasheet(118/219 Pages) AMD

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P R E L I M I N A R Y

118

Am79C970A

and should treat the read value

as undefined.

RES

Reserved location. The default

value of this bit is a ZERO. Writ-

ing a ONE to this bit has no effect

on device function. If a ONE is

written to this bit, then a ONE will

be read back. Existing drivers

may write a ONE to this bit for

compatibility, but new drivers

should write a ZERO to this bit

and should treat the read value

as undefined.

CSR4: Test and Features Control

Bit

Name

Description

Certain bits in CSR4 indicate the

cause of an interrupt. The regis-

ter is designed so that these

indicator bits are cleared by writ-

ing ONEs to those bit locations.

This means that the software can

read CSR4 and write back the

value just read to clear the

interrupt condition.

31–16

RES

Reserved locations. Written as

ZEROs and read as undefined.

EN124

Enable CSR124 access. Setting

EN124 to ONE allows the user to

write to bits in CSR124 which

enable

the

GPSI

interface

(GPSIEN, bit 4) and Runt Packet

Accept mode (RPA, bit 3). Once

these bits are accessed EN124

must be cleared back to ZERO.

Read/Write accessible always.

EN124 is cleared by H_RESET

or S_RESET and is unaffected

by setting the STOP bit.

In order to set EN124, it must be

written with a ONE during the first

write access to CSR4 after

H_RESET or S_RESET. Once a

ZERO is written to this bit

position, EN124 cannot be set

until

after

the

PCnet-PCI

controller is reset by H_RESET

or S_RESET.

DMAPLUS

When DMAPLUS is set to ONE,

the DMA Burst Transfer Counter

CSR80

disabled.

DMAPLUS is cleared to ZERO,

the counter is enabled.

DMAPLUS should be set to ONE

when the PCnet-PCI II controller

is used in a PCI bus application.

Read/Write accessible always.

DMAPLUS

cleared

H_RESET or S_RESET and is

unaffected

setting

the

STOP bit.

TIMER

Enable Bus Activity Timer. If

TIMER is set to ONE, the Bus Ac-

tivity Timer (CSR82) is enabled.

If TIMER is cleared, the Bus Ac-

tivity Timer is disabled.

TIMER should stay at its default

value

ZERO

when

the

PCnet-PCI II controller is used in

a PCI bus application.

Read/Write accessible always.

TIMER is cleared by H_RESET

or S_RESET and is unaffected

by setting the STOP bit.

DPOLL

Disable

Transmit

Polling.

DPOLL is set, the Buffer Man-

agement Unit will disable trans-

mit polling. If DPOLL is cleared,

automatic transmit polling is en-

abled. If DPOLL is set, the TDMD

bit in CSR0 must be set in order

to initiate a manual poll of a

transmit descriptor. transmit de-

scriptor polling will not take place

if TXON is cleared.

Read/Write accessible always.

DPOLL is cleared by H_RESET

or S_RESET and is unaffected

by setting the STOP bit.

APAD_XMT

Auto Pad Transmit. When set,

APAD_XMT enables the auto-

matic padding feature. Transmit

frames will be padded to extend

them to 64 bytes including FCS.

The FCS is calculated for the en-

tire frame including pad, and

appended

after

the

pad.

APAD_XMT will override the pro-

gramming of the DXMTFCS bit

(CSR15, bit 3) and of the

ADD_FCS/NO_FCS bit (TMD1,

bit 29).

Read/Write accessible always.

APAD_XMT

cleared

H_RESET or S_RESET and

is unaffected by setting the

STOP bit.

10 ASTRP_RCV

Auto Strip Receive. When set,

ASTRP_RCV enables the auto-

matic pad stripping feature. The

pad and FCS fields will be

stripped from receive frames and

not placed in the FIFO.

Read/Write accessible always.

ASTRP_RCV

cleared

H_RESET or S_RESET and

is unaffected by setting the

STOP bit.

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