DM163006 datasheet(94/320 Pages) MICROCHIP

94 / 320 page

PIC18C601/801

DS39541A-page 94

Advance Information

 2001 Microchip Technology Inc.

8.1.2

PIR REGISTERS

The Peripheral Interrupt Request (PIR) registers con-

tain the individual flag bits for the peripheral interrupts

(Register 8-5). There are two Peripheral Interrupt

Request (Flag) registers (PIR1, PIR2).

8.1.3

PIE REGISTERS

The Peripheral Interrupt Enable (PIE) registers contain

the individual enable bits for the peripheral interrupts

(Register 8-6). There are two two Peripheral Interrupt

Enable registers (PIE1, PIE2). When IPEN is clear, the

PEIE bit must be set to enable any of these peripheral

interrupts.

8.1.4

IPR REGISTERS

The Interrupt Priority (IPR) registers contain the individ-

ual priority bits for the peripheral interrupts (Register 8-9).

There are two Peripheral Interrupt Priority registers

(IPR1, IPR2). The operation of the priority bits requires

that the Interrupt Priority Enable bit (IPEN) be set.

8.1.5

RCON REGISTER

The Reset Control (RCON) register contains the bit that

is used to enable prioritized interrupts (IPEN).

RCON REGISTER

Note 1: Interrupt flag bits are set when an interrupt

condition occurs, regardless of the state of

its corresponding enable bit, or the global

enable bit, GIE (INTCON register).

2: User software should ensure the appropri-

ate interrupt flag bits are cleared prior to

enabling an interrupt, and after servicing

that interrupt.

R/W-0

U-0

R/W-1

R/W-0

U-0

IPEN

—

POR

bit 7

bit 0

bit 7

IPEN: Interrupt Priority Enable bit

= Enable priority levels on interrupts

= Disable priority levels on interrupts (16CXXX compatibility mode)

bit 6

Reserved: Maintain as '0'

bit 5

Unimplemented: Read as '0'

bit 4

RI: RESET Instruction Flag bit

For details of bit operation, see Register 4-4

bit 3

TO: Watchdog Time-out Flag bit

For details of bit operation, see Register 4-4

bit 2

PD: Power-down Detection Flag bit

For details of bit operation, see Register 4-4

bit 1

POR: Power-on Reset Status bit

For details of bit operation, see Register 4-4

bit 0

Reserved: Maintain as '0'

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

- n = Value at POR

’1’ = Bit is set

’0’ = Bit is cleared

x = Bit is unknown

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