DM163006 datasheet(30/320 Pages) MICROCHIP

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PIC18C601/801

DS39541A-page 30

Advance Information

 2001 Microchip Technology Inc.

3.1

Power-on Reset (POR)

A Power-on Reset pulse is generated on-chip when a

VDD rise is detected. To take advantage of the POR cir-

cuitry, connect the MCLR pin directly (or through a

resistor) to VDD. This will eliminate external RC compo-

nents usually needed to create a Power-on Reset

delay. A minimum rise rate for VDD is specified (param-

eter D004). For a slow rise time, see Figure 3-2.

When the device starts normal operation (exits the

RESET condition), device operating parameters (volt-

age, frequency, temperature, etc.) must be met to

ensure operation. If these conditions are not met, the

device must be held in RESET until the operating con-

ditions are met. Power-on Reset may be used to meet

the voltage start-up condition.

FIGURE 3-2:

EXTERNAL POWER-ON

RESET CIRCUIT (FOR

SLOW VDD POWER-UP)

3.2

Power-up Timer (PWRT)

The Power-up Timer provides a fixed nominal time-out

(parameter #33), only on power-up from the POR. The

Power-up Timer operates on an internal RC oscillator.

The chip is kept in RESET as long as the PWRT is

active. The PWRT time delay allows VDD to rise to an

acceptable level. PIC18C601/801 devices are avail-

able with PWRT enabled or disabled.

The power-up time delay will vary from chip to chip, due

to VDD, temperature and process variation. See DC

parameter #33 for details.

3.3

Oscillator Start-up Timer (OST)

The Oscillator Start-up Timer (OST) provides 1024

oscillator cycle (from OSC1 input) delay after the

PWRT delay is over (parameter #32). This ensures that

the crystal oscillator or resonator has started and

stabilized.

The OST time-out is invoked only for LP, HS and HS4

modes and only on Power-on Reset or wake-up from

SLEEP.

3.4

PLL Lock Time-out

With the PLL enabled, the time-out sequence following

a Power-on Reset is different from other oscillator

modes. A portion of the Power-up Timer is used to pro-

vide a fixed time-out that is sufficient for the PLL to lock

to the main oscillator frequency. This PLL lock time-out

(TPLL) is typically 1 ms and follows the oscillator start-

up time-out (OST).

3.5

Time-out Sequence

On power-up, the time-out sequence is as follows:

First, PWRT time-out is invoked after the POR time

delay has expired; then, OST is activated. The total

time-out will vary based on oscillator configuration and

the status of the PWRT. For example, in RC mode with

the PWRT disabled, there will be no time-out at all.

Figure 3-3, Figure 3-4, Figure 3-5, Figure 3-6 and

Figure 3-7 depict time-out sequences on power-up.

Since the time-outs occur from the POR pulse, if MCLR

is kept low long enough, the time-outs will expire.

Bringing MCLR high will begin execution immediately

(Figure 3-5). This is useful for testing purposes or to

synchronize more than one PIC18C601/801 device

operating in parallel.

Table 3-2 shows the RESET conditions for some

Special Function Registers, while Table 3-3 shows the

RESET conditions for all registers.

Note 1: External Power-on Reset circuit is required only

if the VDD power-up slope is too slow. The diode

D helps discharge the capacitor quickly when

VDD powers down.

2: R < 40 k

Ω is recommended to make sure that

the voltage drop across R does not violate the

device’s electrical specification.

3: R1 = 100

Ω to 1 kΩ will limit any current flowing

into MCLR from external capacitor C, in the

event of MCLR/VPP pin breakdown due to

Electrostatic Discharge (ESD), or Electrical

Overstress (EOS).

VDD

MCLR

PIC18C601/801

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