DM163006 datasheet(28/320 Pages) MICROCHIP

28 / 320 page

PIC18C601/801

DS39541A-page 28

Advance Information

 2001 Microchip Technology Inc.

FIGURE 2-10:

TIMING FOR TRANSITION BETWEEN TIMER1 AND OSC1 (RC, EC)

2.6.3

SCS0, SCS1 PRIORITY

If both SCS0 and SCS1 are set to ‘1’ simultaneously,

the SCS0 bit has priority over the SCS1 bit. This means

that the low power option will take precedence over the

PLL option. If both bits are cleared simultaneously, the

system clock will come from OSC1, after a TOST time-

out. If only the SCS0 bit is cleared, the system clock will

come from the PLL output, following TOST and TPLL

time.

TABLE 2-3:

SCS0, SCS1 PRIORITY

2.7

Effects of SLEEP Mode on the

On-Chip Oscillator

When the device executes a SLEEP instruction, the

on-chip clocks and oscillator are turned off and the

device is held at the beginning of an instruction cycle

(Q1 state). With the oscillator off, the OSC1 and OSC2

signals will stop oscillating. Since all the transistor

switching currents have been removed, SLEEP mode

achieves the lowest current consumption of the device

(only leakage currents). Enabling any on-chip feature

that will operate during SLEEP, will increase the cur-

rent consumed during SLEEP. The user can wake from

SLEEP through external RESET, Watchdog Timer

Reset, or through an interrupt.

2.8

Power-up Delays

Power-up delays are controlled by two timers, so that

no external RESET circuitry is required for most appli-

cations. The delays ensure that the device is kept in

RESET until the device power supply and clock are sta-

ble. For additional information on RESET operation,

see Section 3.0 RESET.

The first timer is the Power-up Timer (PWRT), which

optionally provides a fixed delay of TPWRT (parameter

#33) on power-up only. The second timer is the Oscil-

lator Start-up Timer (OST), intended to keep the chip in

RESET until the crystal oscillator is stable.

PIC18C601/801 devices provide a configuration bit,

PWRTEN in CONFIG2L register, to enable or disable

the Power-up Timer. By default, the Power-up Timer is

enabled.

With the PLL enabled (HS4 oscillator mode), the time-out

sequence following a Power-on Reset is different from

other oscillator modes. The time-out sequence is as fol-

lows: the PWRT time-out is invoked after a POR time

delay has expired, then, the Oscillator Start-up Timer

(OST) is invoked. However, this is still not a sufficient

amount of time to allow the PLL to lock at high frequen-

cies. The PWRT timer is used to provide an additional

time-out, called TPLL (parameter #7), to allow the PLL

ample time to lock to the incoming clock frequency.

TABLE 2-4:

OSC1 AND OSC2 PIN STATES IN SLEEP MODE

Q1 Q2

Q4 Q1 Q2 Q3

OSC1

Internal System

SCS0

(OSCCON<0>)

Program Counter

PC + 2

Note:

RC oscillator mode assumed.

PC + 4

T1OSI

Clock

OSC2

TT1P

TOSC

TSCS

SCS1

SCS0

Clock Source

Ext Oscillator OSC1

Timer1 Oscillator

HS + PLL

Timer1 Oscillator

OSC Mode

OSC1 Pin

OSC2 Pin

Floating, external resistor should pull high

At logic low

Floating

At logic low

LP and HS Feedback inverter disabled, at quiescent voltage level Feedback inverter disabled, at quiescent voltage level

Note:

See Table 3-1 in Section 3.0 RESET, for time-outs due to SLEEP and MCLR Reset.

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