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DM163006 датащи(PDF) 35 Page - Microchip Technology |
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DM163006 датащи(HTML) 35 Page - Microchip Technology |
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35 / 320 page ![]() 2001 Microchip Technology Inc. Advance Information DS39541A-page 35 PIC18C601/801 POSTINC2 601 801 (Note 5) (Note 5) (Note 5) POSTDEC2 601 801 (Note 5) (Note 5) (Note 5) PREINC2 601 801 (Note 5) (Note 5) (Note 5) PLUSW2 601 801 (Note 5) (Note 5) (Note 5) FSR2H 601 801 ---- 0000 ---- 0000 ---- uuuu FSR2L 601 801 xxxx xxxx uuuu uuuu uuuu uuuu STATUS 601 801 ---x xxxx ---u uuuu ---u uuuu TMR0H 601 801 xxxx xxxx uuuu uuuu uuuu uuuu TMR0L 601 801 xxxx xxxx uuuu uuuu uuuu uuuu T0CON 601 801 1111 1111 1111 1111 uuuu uuuu OSCCON 601 801 --00 0-00 --uu u-u0 --uu u-uu LVDCON 601 801 --00 0101 --00 0101 --uu uuuu WDTCON 601 801 ---- 1111 ---- uuuu ---- uuuu RCON(4) 601 801 0r-1 11qr 0r-1 qqur ur-u qqur TMR1H 601 801 xxxx xxxx uuuu uuuu uuuu uuuu TMR1L 601 801 xxxx xxxx uuuu uuuu uuuu uuuu T1CON 601 801 0-00 0000 u-uu uuuu u-uu uuuu TMR2 601 801 xxxx xxxx uuuu uuuu uuuu uuuu PR2 601 801 1111 1111 1111 1111 1111 1111 T2CON 601 801 -000 0000 -000 0000 -uuu uuuu SSPBUF 601 801 xxxx xxxx uuuu uuuu uuuu uuuu SSPADD 601 801 0000 0000 0000 0000 uuuu uuuu SSPSTAT 601 801 0000 0000 0000 0000 uuuu uuuu SSPCON1 601 801 0000 0000 0000 0000 uuuu uuuu SSPCON2 601 801 0000 0000 0000 0000 uuuu uuuu ADRESH 601 801 xxxx xxxx uuuu uuuu uuuu uuuu ADRESL 601 801 xxxx xxxx uuuu uuuu uuuu uuuu ADCON0 601 801 --00 0000 --00 0000 --uu uuuu ADCON1 601 801 -000 0000 -000 0000 -uuu uuuu ADCON2 601 801 0--- -000 0--- -000 u--- -uuu CCPR1H 601 801 xxxx xxxx uuuu uuuu uuuu uuuu CCPR1L 601 801 xxxx xxxx uuuu uuuu uuuu uuuu CCP1CON 601 801 --00 0000 --00 0000 --uu uuuu TABLE 3-3: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Register Applicable Devices Power-on Reset MCLR Reset WDT Reset Reset Instruction Stack Over/Underflow Reset Wake-up via WDT or Interrupt Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ’0’, q = value depends on condition, r = reserved, maintain ‘0’ Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (00008h or 00018h). 3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH, and TOSL are updated with the current value of the PC. The SKPTR is modified to point to the next location in the hardware stack. 4: See Table 3-2 for RESET value for specific condition. 5: This is not a physical register. It is an indirect pointer that addresses another register. The contents returned is the value contained in the addressed register. |
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