DM163006 datasheet(65/320 Pages) MICROCHIP

65 / 320 page

 2001 Microchip Technology Inc.

Advance Information

DS39541A-page 65

PIC18C601/801

FIGURE 5-2:

8-BIT MULTIPLEXED MODE TIMING

5.2.2

8-BIT DE-MULTIPLEXED MODE

The 8-bit De-Multiplexed mode applies only to the

PIC18C801. Data and address lines are available sep-

arately. External components are not necessary in this

mode.

For 8-bit De-Multiplexed mode on the PIC18C801, the

instructions are fetched as two 8-bit bytes on a dedi-

cated data bus (PORTJ). The address will be pre-

sented for the entire duration of the fetch cycle on a

separate address bus. The two instruction bytes are

sequentially fetched within one instruction cycle (TCY).

Therefore, the designer must choose external memory

devices according to timing calculations, based on 1/2

TCY (2 times instruction rate). For proper memory speed

selection, setup and hold times must be considered.

The Address Latch Enable (ALE) pin is left uncon-

nected, since glue logic is not necessary. The OE out-

put enable signal will enable one byte of program

memory for a portion of the instruction cycle, then BA0

will change and the second byte will be enabled to form

the 16-bit instruction word. The least significant bit of

the address, BA0, must be connected to the memory

devices in this mode. Figure 5-3 shows an example of

8-bit De-Multiplexed mode on the PIC18C801. The

control signals used in 8-bit De-Multiplexed mode are

outlined in Register 5-2. Register 5-4 describes 8-bit

De-Multiplexed mode timing.

A16, AD<15:8>

ALE

AD<7:0>

BA0

Opcode Fetch

MOVLW 55h

from 007556h

03Ah

ABh

55h

0Eh

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