DM163006 datasheet(46/320 Pages) MICROCHIP

46 / 320 page

PIC18C601/801

DS39541A-page 46

Advance Information

 2001 Microchip Technology Inc.

4.4

PCL, PCLATH and PCLATU

The program counter (PC) specifies the address of the

instruction to fetch for execution. The PC is 21-bits

wide. The low byte is called the PCL register. This reg-

ister is readable and writable. The high byte is called

the PCH register. This register contains the PC<15:8>

bits and is not directly readable or writable. Updates to

the PCH register may be performed through the

PCLATH register. The upper byte is called PCU. This

readable or writable. Updates to the PCU register may

be performed through the PCLATU register.

The PC addresses bytes in the program memory. To

prevent the PC from becoming misaligned with word

instructions, the LSb of the PCL is fixed to a value of ’0’.

The PC increments by 2 to address sequential instruc-

tions in the program memory.

The CALL,

RCALL,

GOTO

and program branch

instructions write to the program counter directly. For

these instructions, the contents of PCLATH and

PCLATU are not transferred to the program counter.

The contents of PCLATH and PCLATU will be trans-

ferred to the program counter by an operation that

writes PCL. Similarly, the upper two bytes of the pro-

gram counter will be transferred to PCLATH and

PCLATU by an operation that reads PCL. This is useful

for computed offsets to the PC (See Section 4.8.1).

4.5

Clocking Scheme/Instruction

Cycle

The clock input (from OSC1 or PLL output) is internally

divided by four to generate four non-overlapping

quadrature clocks, namely Q1, Q2, Q3 and Q4. Inter-

nally, the program counter (PC) is incremented every

Q1, the instruction is fetched from the program memory

and latched into the instruction register in Q4. The

instruction is decoded and executed during the follow-

ing Q1 through Q4. The clocks and instruction execu-

tion flow are shown in Figure 4-6.

FIGURE 4-6:

CLOCK/INSTRUCTION CYCLE

OSC1

OSC2/CLKOUT

(RC mode)

PC+2

PC+4

Fetch INST (PC)

Execute INST (PC-2)

Fetch INST (PC+2)

Execute INST (PC)

Fetch INST (PC+4)

Execute INST (PC+2)

Internal

Phase

Clock

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