DM163006 datasheet(91/320 Pages) MICROCHIP

91 / 320 page

 2001 Microchip Technology Inc.

Advance Information

DS39541A-page 91

PIC18C601/801

8.1

Control Registers

This section contains the control and status registers.

8.1.1

INTCON REGISTERS

The INTCON Registers are readable and writable

registers, which contain various enable, priority, and

flag bits.

INTCON REGISTER

R/W-0

R/W-x

GIE/GIEH PEIE/GIEL

TMR0IE

INT0IE

RBIE

TMR0IF

INT0IF

RBIF

bit 7

bit 0

bit 7

GIE/GIEH: Global Interrupt Enable bit

When IPEN = 0:

= Enables all unmasked interrupts

= Disables all interrupts

When IPEN = 1:

= Enables all high priority interrupts

= Disables all high priority interrupts

bit 6

PEIE/GIEL: Peripheral Interrupt Enable bit

When IPEN = 0:

= Enables all unmasked peripheral interrupts

= Disables all peripheral interrupts

When IPEN = 1:

= Enables all low priority peripheral interrupts

= Disables all priority peripheral interrupts

bit 5

TMR0IE: TMR0 Overflow Interrupt Enable bit

= Enables the TMR0 overflow interrupt

= Disables the TMR0 overflow interrupt

bit 4

INT0IE: INT0 External Interrupt Enable bit

= Enables the INT0 external interrupt

= Disables the INT0 external interrupt

bit 3

RBIE: RB Port Change Interrupt Enable bit

= Enables the RB port change interrupt

= Disables the RB port change interrupt

bit 2

TMR0IF: TMR0 Overflow Interrupt Flag bit

= TMR0 register has overflowed (must be cleared in software)

= TMR0 register did not overflow

bit 1

INT0IF: INT0 External Interrupt Flag bit

= The INT0 external interrupt occurred (must be cleared in software)

= The INT0 external interrupt did not occur

bit 0

RBIF: RB Port Change Interrupt Flag bit

= At least one of the RB7:RB4 pins changed state (must be cleared in software)

= None of the RB7:RB4 pins have changed state

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

- n = Value at POR

’1’ = Bit is set

’0’ = Bit is cleared

x = Bit is unknown

Note:

Interrupt flag bits get set when an interrupt condition occurs, regardless of the state

of its corresponding enable bit, or the global enable bit. User software should ensure

the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature

allows software polling.

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