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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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AM3703CUS датащи(PDF) 214 Page - Texas Instruments |
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AM3703CUS датащи(HTML) 214 Page - Texas Instruments |
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214 / 280 page  AM3715, AM3703 SPRS616F – JUNE 2010 – REVISED AUGUST 2011 www.ti.com (1) In mcbspx, x identifies the McBSP number: 1, 2, or 3. Note that for the McBSP3, these timings concern only Set #2 (multiplexing mode on UART pins) and Set #3 (multiplexing mode on McBSP1 pins). (2) See Section 4.3.4, Processor Clocks. Table 6-48. McBSP1, 2, and 3 (Sets #2 and #3) Switching Characteristics —Rising Edge and Receive Mode(1) (2) NO. PARAMETER OPP100 OPP50 UNIT MIN MAX MIN MAX B2 td(CLKAE-FSV) Delay time, mcbsp1_clkr / mcbspx_clkx active edge to 0.7 14.79 0.7 29.58 ns mcbsp1_fsr / mcbspx_fsx valid (1) In mcbspx, x identifies the McBSP number: 1, 2, or 3. Note that for the McBSP3, these timings concern only Set #2 (multiplexing mode on UART pins) and Set #3 (multiplexing mode on McBSP1 pins). (2) See Section 4.3.4, Processor Clocks. Table 6-49. McBSP4 (Set #1) Timing Requirements —Rising Edge and Receive Mode(1) (2) NO. PARAMETER OPP100 OPP50 UNIT MIN MAX MIN MAX B3 tsu(DRV-CLKXAE) Setup time, mcbspx_dr valid before Master 2.87 8.63 ns mcbspx_clkx active edge Slave 3.67 7.94 ns B4 th(CLKXAE-DRV) Hold time, mcbspx_dr valid after Master 1.01 1.01 ns mcbspx_clkx active edge Slave 0.4 0.4 ns B5 tsu(FSXV-CLKXAE) Setup time, mcbspx_fsx valid before mcbspx_clkx 3.67 7.94 ns active edge B6 th(CLKXAE-FSXV) Hold time, mcbspx_fsx valid after mcbspx_clkx active 0.5 0.5 ns edge (1) In mcbspx, x identifies the McBSP number: 4. Note that for the McBSP4, these timings concern only Set #1: multiplexing mode by default. The McBSP4 is also multiplexed on GPMC pins (Set #2): the corresponding timings are specified in Table 6-51 and Table 6-52. (2) See Section 4.3.4, Processor Clocks. Table 6-50. McBSP4 (Set #1) Switching Characteristics —Rising Edge and Receive Mode(1) (2) NO. PARAMETER OPP100 OPP50 UNIT MIN MAX MIN MAX B2 td(CLKXAE-FSXV) Delay time, mcbspx_clkx active edge to mcbspx_fsx 0.7 16.56 0.7 33.12 ns valid (1) In mcbspx, x identifies the McBSP number: 4. Note that for the McBSP4, these timings concern only Set #1: multiplexing mode by default. The McBSP4 is also multiplexed on GPMC pins (Set #2): the corresponding timings are specified in Table 6-51 and Table 6-52. (2) See Section 4.3.4, Processor Clocks. Table 6-51. McBSP3 (Set #1), 4 (Set #2), and 5 Timing Requirements —Rising Edge and Receive Mode(1) (2) NO. PARAMETER OPP100 OPP50 UNIT MIN MAX MIN MAX B3 tsu(DRV-CLKXAE) Setup time, mcbspx_dr valid before Master 6.49 12.90 ns mcbspx_clkx active edge Slave 5.80 12.21 ns B4 th(CLKXAE-DRV) Hold time, mcbspx_dr valid after Master 1.01 1.01 ns mcbspx_clkx active edge Slave 0.4 0.4 ns B5 tsu(FSXV-CLKXAE) Setup time, mcbspx_fsx valid before mcbspx_clkx 5.81 12.21 ns active edge B6 th(CLKXAE-FSXV) Hold time, mcbspx_fsx valid after mcbspx_clkx active 0.5 0.5 ns edge 214 Timing Requirements and Switching Characteristics Copyright © 2010–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): AM3715 AM3703 |
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