AM3703CUS datasheet(210/280 Pages) TI

210 / 280 page

AM3715, AM3703

SPRS616F

– JUNE 2010 – REVISED AUGUST 2011

www.ti.com

Table 6-44. DSS Switching Characteristics

—RFBI Mode—Pico DLP(15)(17)(18)

PARAMETER

OPP100

OPP50

UNIT

MIN

MAX

MIN

MAX

tw(wrH)

Pulse duration, output write enable rfbi_wr high

A(1)

tw(wrL)

Pulse duration, output write enable rfbi_wr low

B(2)

td(a0-wrL)

Delay time, output command/data control rfbi_a0

C(3)

transition to output write enable rfbi_wr low

td(wrH-a0)

Delay time, output write enable rfbi_wr high to output

D(4)

command/data control rfbi_a0 transition

td(csx-wrL)

Delay time, output chip select rfbi_csx(14) low to output

E(5)

write enable rfbi_wr low

td(wrH-csxH)

Delay time, output write enable rfbi_wr high to output

F(6)

chip select rfbi_csx(14) high

td(dataV)

Output data rfbi_da[15:0](16) valid

G(7)

td(Skew)

Skew between output write enable falling rfbi_wr and

15.5

output data rfbi_da[15:0](16) high or low

td(a0H-rdL)

Delay time, output command/data control rfbi_a0 high to

H(8)

output read enable rfbi_rd low

td(rdlH-a0)

Delay time, output read enable rfbi_rd high to output

I(9)

command/data control rfbi_a0 transition

tw(rdH)

Pulse duration, output read enable rfbi_rd high

J(10)

tw(rdL)

Pulse duration, output read enable rfbi_rd low

K(11)

td(rdL-csxL)

Delay time, output read enable rfbi_rd low to output chip

L(12)

select rfbi_csx(14) low

td(rdL-csxH)

Delay time, output read enable rfbi_rd low to output chip

M(13)

select rfbi_csx(14) high

tR(wr)

Rise time, output write enable rfbi_wr

tF(wr)

Fall time, output write enable rfbi_wr

tR(a0)

Rise time, output command/data control rfbi_a0

tF(a0)

Fall time, output command/data control rfbi_a0

tR(csx)

Rise time, output chip select rfbi_csx(14)

tF(csx)

Fall time, output chip select rfbi_csx(14)

tR(d)

Rise time, output data rfbi_da[15:0](16)

tF(d)

Fall time, output data rfbi_da[15:0](16)

tR(rd)

Rise time, output read enable rfbi_rd

tF(rd)

Fall time, output read enable rfbi_rd

CsOnTime

CS signal assertion time from Start Access Time -

0(19)

RFBI_ONOFF_TIMEi Register

CsOffTime

CS signal de-assertion time from Start Access Time -

40(19)

RFBI_ONOFF_TIMEi Register

WeOnTime

WE signal assertion time from Start Access Time -

0(19)

RFBI_ONOFF_TIMEi Register

WeOffTime

WE signal de-assertion time from Start Access Time -

20(19)

RFBI_ONOFF_TIMEi Register

ReOnTime

RE signal assertion time from Start Access Time -

RFBI_ONOFF_TIMEi Register

ReOffTime

RE signal de-assertion time from Start Access Time -

RFBI_ONOFF_TIMEi Register

WeCycleTime

Write cycle time - RFBI_CYCLE_TIMEi Register

40(19)

ReCycleTime

Read cycle time - RFBI_CYCLE_TIMEi Register

CsPulseWidth

CS pulse width - RFBI_CYCLE_TIMEi Register

0(19)

210

Timing Requirements and Switching Characteristics

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