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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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AM3703CUS датащи(PDF) 213 Page - Texas Instruments |
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AM3703CUS датащи(HTML) 213 Page - Texas Instruments |
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213 / 280 page  AM3715, AM3703 www.ti.com SPRS616F – JUNE 2010 – REVISED AUGUST 2011 Table 6-46. McBSP Output Clock Characteristics —Normal Mode(4) PARAMETER OPP100 OPP50 UNIT MIN MAX MIN MAX McBSP1 tc(CLK) Cycle time, mcbsp1_clkx (multiplexing mode 0) / 48 24 MHz mcbsp1_clkr (multiplexing mode 0 & 2) McBSP2 tc(CLK) Cycle time, mcbsp2_clkx (multiplexing mode 0) 48 24 MHz McBSP3 tc(CLK) Cycle time, mcbsp3_clkx IO set 1 32 16 MHz (multiplexing mode 0) IO set 2 48 24 (multiplexing mode 1) IO set 3 48 24 (multiplexing mode 2) McBSP4 tc(CLK) Cycle time, mcbsp4_clkx IO set 1 48 16 MHz (multiplexing mode 0) IO set 3 32 16 (multiplexing mode 2) McBSP5 tc(CLK) Cycle time, mcbsp5_clkx IO set 2 32 16 MHz (multiplexing mode 1) tW(CLKH) Typical pulse duration, mcbsp1_clkr / mcbspx_clkx high(2) 0.5*P(1) 0.5*P(1) ns tW(CLKL) Typical pulse duration, mcbsp1_clkr / mcbspx_clkx low(2) 0.5*P(1) 0.5*P(1) ns tdc(CLK) Duty cycle error, mcbsp1_clkr / mcbspx_clkx(2) –0.75 0.75 –0.75 0.75 ns Jitter, mcbsp1_clkr / mcbspx_clkx(3) / mcbsp_clks -0.40 0.40 -0.40 0.40 ns (1) P = mcbspy_clkx(2) or mcbsp1_clkr output clock period in ns (2) In mcbspy, y is equal to 1, 2, 3, 4, or 5. (3) In mcbspx, x identifies the McBSP number: 1, 2, 3, 4, or 5. (4) See Section 4.3.4, Processor Clocks. 6.6.1.1.1 Rising Edge as Activation Mode 6.6.1.1.1.1 Timing with Rising Edge as Activation Edge —Receive Mode Table 6-47. McBSP1, 2, and 3 (Sets #2 and #3) Timing Requirements —Rising Edge and Receive Mode(1) (2) NO. PARAMETER OPP100 OPP50 UNIT MIN MAX MIN MAX B3 tsu(DRV-CLKAE) Setup time, mcbspx_dr valid before Master 4.36 8.63 ns mcbsp1_clkr / mcbspx_clkx active edge Slave 3.67 7.94 ns B4 th(CLKAE-DRV) Hold time, mcbspx_dr valid after Master 1.01 1.01 ns mcbsp1_clkr / mcbspx_clkx active edge Slave 0.4 0.4 ns B5 tsu(FSV-CLKAE) Setup time, mcbsp1_fsr / mcbspx_fsx valid before 3.67 7.94 ns mcbsp1_clkr / mcbspx_clkx active edge B6 th(CLKAE-FSV) Hold time, mcbsp1_fsr / mcbspx_fsx valid after 0.5 0.5 ns mcbsp1_clkr / mcbspx_clkx active edge Copyright © 2010–2011, Texas Instruments Incorporated Timing Requirements and Switching Characteristics 213 Submit Documentation Feedback Product Folder Link(s): AM3715 AM3703 |
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