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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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AM3703CUS датащи(PDF) 217 Page - Texas Instruments |
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AM3703CUS датащи(HTML) 217 Page - Texas Instruments |
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217 / 280 page  SWPS038-064 mcbspx_clkx mcbspx_fsx mcbspx_dx D7 D6 D5 B2 B2 B8 SWPS038-065 mcbspx_clkx mcbspx_fsx mcbspx_dx D7 D6 D5 B8 B5 B6 AM3715, AM3703 www.ti.com SPRS616F – JUNE 2010 – REVISED AUGUST 2011 Table 6-58. McBSP3 (Set #1), 4 (Set #2), and 5 Switching Characteristics —Rising Edge and Transmit Mode(1) (2) NO. PARAMETER OPP100 OPP50 UNIT MIN MAX MIN MAX B2 td(CLKXAE-FSXV) Delay time, mcbspx_clkx active edge to mcbspx_fsx 0.7 22.18 0.7 44.37 ns valid B8 td(CLKXAE-DXV) Delay time, mcbspx_clkx active edge to Master 0.6 21.28 0.6 43.47 ns mcbspx_dx valid Slave 0.6 21.28 0.6 43.47 ns (1) In mcbspx, x identifies the McBSP number: 3, 4, or 5. Note that for the McBSP3, these timings concern only Set #1: multiplexing mode by default. The McBSP3 is also multiplexed on UART pins (Set #2) and on McBSP1 pins (Set #3): the corresponding timings are specified in Table 6-53 and Table 6-54. For the McBSP4, these timings concern only Set #2 (multiplexing mode on GPMC pins). (2) See Section 4.3.4, Processor Clocks. (1) In mcbspx, x identifies the McBSP number: 1, 2, 3, 4, or 5. Figure 6-38. McBSP Rising Edge Transmit Timing in Master Mode (1) In mcbspx, x identifies the McBSP number: 1, 2, 3, 4, or 5. Figure 6-39. McBSP Rising Edge Transmit Timing in Slave Mode 6.6.1.1.2 Falling Edge as Activation Edge 6.6.1.1.2.1 Timing with Falling Edge as Activation Edge Mode —Receive Mode Table 6-59. McBSP1, 2, 3 (Sets #2 and #3) Timing Requirements —Falling Edge and Receive Mode(1) (2) NO. PARAMETER OPP100 OPP50 UNIT MIN MAX MIN MAX B3 tsu(DRV-CLKAE) Setup time, mcbspx_dr valid before Master 4.36 8.63 ns mcbsp1_clkr / mcbspx_clkx active edge Slave 3.67 7.94 ns B4 th(CLKAE-DRV) Hold time, mcbspx_dr valid after Master 1.01 1.01 ns mcbsp1_clkr / mcbspx_clkx active edge Slave 0.4 0.4 ns B5 tsu(FSV-CLKAE) Setup time, mcbsp1_fsr / mcbspx_fsx valid before 3.7 7.94 ns mcbsp1_clkr / mcbspx_clkx active edge B6 th(CLKAE-FSV) Hold time, mcbsp1_fsr / mcbspx_fsx valid after 0.5 0.5 ns mcbsp1_clkr / mcbspx_clkx active edge Copyright © 2010–2011, Texas Instruments Incorporated Timing Requirements and Switching Characteristics 217 Submit Documentation Feedback Product Folder Link(s): AM3715 AM3703 |
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