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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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AM3703CUS датащи(PDF) 48 Page - Texas Instruments |
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AM3703CUS датащи(HTML) 48 Page - Texas Instruments |
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48 / 280 page  AM3715, AM3703 SPRS616F – JUNE 2010 – REVISED AUGUST 2011 www.ti.com Table 2-2. Ball Characteristics (CBC Pkg.)(5) (continued) BALL BALL TOP PIN NAME [2] MODE [3] TYPE [4] BALL BALL RESET RESET POWER [8] HYS [9] BUFFER PULLUP IO CELL BOTTOM [1] RESET REL. STATE REL. MODE STRENGTH /DOWN [12] [1] STATE [5] [6] [7] (mA) [10] TYPE [11] gpio_38 4 IO safe_mode 7 - F2 NA gpmc_a6 0 O H H 7 vdds Yes 8 PU/ PD LVCMOS gpio_39 4 IO safe_mode 7 - E1 NA gpmc_a7 0 O H H 7 vdds Yes 8 PU/ PD LVCMOS gpio_40 4 IO safe_mode 7 - E2 NA gpmc_a8 0 O H H 7 vdds Yes 8 PU/ PD LVCMOS gpio_41 4 IO safe_mode 7 - D1 NA gpmc_a9 0 O H H 7 vdds Yes 8 PU/ PD LVCMOS sys_ndmareq2 1 I gpio_42 4 IO safe_mode 7 - D2 NA gpmc_a10 0 O H H 7 vdds Yes 8 PU/ PD LVCMOS sys_ndmareq3 1 I gpio_43 4 IO safe_mode 7 - N1 L1 gpmc_clk 0 O L 0 0 vdds Yes 8 PU/ PD LVCMOS gpio_59 4 IO safe_mode 7 - AA2 U2 gpmc_d0 0 IO H H 0 vdds Yes 8 PU/ PD LVCMOS AA1 U1 gpmc_d1 0 IO H H 0 vdds Yes 8 PU/ PD LVCMOS AC2 V2 gpmc_d2 0 IO H H 0 vdds Yes 8 PU/ PD LVCMOS AC1 V1 gpmc_d3 0 IO H H 0 vdds Yes 8 PU/ PD LVCMOS AE5 AA3 gpmc_d4 0 IO H H 0 vdds Yes 8 PU/ PD LVCMOS AD6 AA4 gpmc_d5 0 IO H H 0 vdds Yes 8 PU/ PD LVCMOS AD5 Y3 gpmc_d6 0 IO H H 0 vdds Yes 8 PU/ PD LVCMOS AC5 Y4 gpmc_d7 0 IO H H 0 vdds Yes 8 PU/ PD LVCMOS V1 R1 gpmc_d8 0 IO H H 0 vdds Yes 8 PU/ PD LVCMOS gpio_44 4 IO safe_mode 7 - Y1 T1 gpmc_d9 0 IO H H 0 vdds Yes 8 PU/ PD LVCMOS gpio_45 4 IO safe_mode 7 - T1 N1 gpmc_d10 0 IO H H 0 vdds Yes 8 PU/ PD LVCMOS gpio_46 4 IO safe_mode 7 - U2 P2 gpmc_d11 0 IO H H 0 vdds Yes 8 PU/ PD LVCMOS gpio_47 4 IO safe_mode 7 - U1 P1 gpmc_d12 0 IO H H 0 vdds Yes 8 PU/ PD LVCMOS gpio_48 4 IO safe_mode 7 - P1 M1 gpmc_d13 0 IO H H 0 vdds Yes 8 PU/ PD LVCMOS gpio_49 4 IO safe_mode 7 - L2 J2 gpmc_d14 0 IO H H 0 vdds Yes 8 PU/ PD LVCMOS gpio_50 4 IO safe_mode 7 - M2 K2 gpmc_d15 0 IO H H 0 vdds Yes 8 PU/ PD LVCMOS gpio_51 4 IO safe_mode 7 - AD10 AA9 gpmc_nadv_ale 0 O 0 0 0 vdds NA 8 NA LVCMOS 48 TERMINAL DESCRIPTION Copyright © 2010–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): AM3715 AM3703 |
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