AM3703CUS datasheet(211/280 Pages) TI

211 / 280 page

swps038-118

rfbi_hsync[1:0]

rfbi_a0

rfbi_csx

rfbi_wr

rfbi_da[n:0]

rfbi_rd

rfbi_te_vsync[1:0]

DATA0

DATA1

CsOnTime

CsOffTime

WeOffTime

CsOnTime

CsOffTime

WeOnTime

WeOffTime

CsPulseWidth

WeCycleTime

WeOnTime

WeCycleTime

AM3715, AM3703

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SPRS616F

– JUNE 2010 – REVISED AUGUST 2011

(1) A = (WECycleTime

– WEOffTime) * (TimeParaGranularity + 1) * L4CLK

(2) B = (WEOffTime

– WEOntime) * (TimeParaGranularity + 1) * L4CLK

(3) C = WEOnTime * (TimeParaGranularity + 1) * L4CLK

(4) D = (WECycleTime + CSPulseWidth

– WEOffTime) * (TimeParaGranularity + 1) * L4CLK if mode Write to Read or Read to Write is

enabled.

(5) E = (WEOnTime

– CSOnTime) * (TimeParaGranularity + 1) * L4CLK

(6) F = (CSOffTime

– WEOffTime) * (TimeParaGranularity + 1) * L4CLK

(7) G = WECycleTime * (TimeParaGranularity + 1) * L4CLK

(8) H = REOnTime * (TimeParaGranularity + 1) * L4CLK

(9) I = (RECycleTime + CSPulseWidth

– REOffTime) * (TimeParaGranularity + 1) * L4CLK if mode Write to Read or Read to Write is

enabled.

(10) J = (RECycleTime

– REOffTime) * (TimeParaGranularity + 1) * L4CLK

(11) K = (REOffTime

– REOntime) * (TimeParaGranularity + 1) * L4CLK

(12) L = (REOnTime

– CSOnTime) * (TimeParaGranularity + 1) * L4CLK

(13) M = (CSOffTime

– REOffTime) * (TimeParaGranularity + 1) * L4CLK

(14) In rfbi_csx, x is equal to 0 or 1.

(15) See Section 4.3.4, Processor Clocks.

(16) 16-bit parallel output interface is selected in DSS register.

(17) At OPP100, L4 clock is 100 MHz and at OPP50, L4 clock is 50 MHz.

(18) rfbi_wr must be at 25 MHz.

(19) These values are calculated by the following formula: RFBI Register (Value) * L4 Clock (ns).

Figure 6-35. DSS

—RFBI Mode—Pico DLP—Command / Data Write(1)(2)

(1) In rfbi_csx, x is equal to 0 or 1.

(2) rfbi_da[n:0], n up to 15

Timing Requirements and Switching Characteristics

211

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