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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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VMV3 датащи(PDF) 149 Page - Microsemi Corporation |
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VMV3 датащи(HTML) 149 Page - Microsemi Corporation |
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149 / 212 page  Military ProASIC3/EL Low Power Flash FPGAs Revision 3 2-135 Table 2-206 • RAM512X18 Military-Case Conditions: TJ = 125°C, VCC = 1.425 V for A3PE600L and A3PE3000L Parameter Description –1 Std. Units tAS Address setup time 0.26 0.31 ns tAH Address hold time 0.00 0.00 ns tENS REN_B, WEN_B setup time 0.10 0.11 ns tENH REN_B, WEN_B hold time 0.06 0.07 ns tDS Input data (DI) setup time 0.19 0.23 ns tDH Input data (DI) hold time 0.00 0.00 ns tCKQ1 Clock High to new data valid on DO (output retained, WMODE = 0) 2.29 2.69 ns tCKQ2 Clock High to new data valid on DO (pipelined) 0.95 1.12 ns tC2CRWH Address collision clk-to-clk delay for reliable read access after write on same address – applicable to opening edge 0.18 0.21 ns tC2CWRH Address collision clk-to-clk delay for reliable write access after read on same address – applicable to opening edge 0.21 0.25 ns tRSTBQ RESET_B Low to data out Low on DO (flow through) 0.98 1.15 ns RESET_B Low to data out Low on DO (pipelined) 0.98 1.15 ns tREMRSTB RESET_B removal 0.30 0.36 ns tRECRSTB RESET_B recovery 1.59 1.87 ns tMPWRSTB RESET_B minimum pulse width 0.59 0.67 ns tCYC Clock cycle time 5.39 6.20 ns FMAX Maximum frequency 185 161 MHz Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values. |
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