AD1981B

Rev. C | Page 23 of 32

Bit

Mnemonic

Function

SPCV

SPDIF Configuration Valid

(Read-Only)

This bit indicates the status of the SPDIF transmitter subsystem, enabling the driver to

determine if the currently programmed SPDIF configuration is supported. SPCV is always valid,

independent of the SPDIF enable bit status.

SPCV = 0 indicates that the current SPDIF configuration (SPSA, SPSR, DAC slot rate, DRS) is not

valid (not supported).

SPCV = 1 indicates that the current SPDIF configuration (SPSA, SPSR, DAC slot rate, DRS) is valid

(supported).

VFORCE

Validity Force Bit

(Reset Default = 0)

When asserted, this bit forces the SPDIF stream validity flag (Bit 28 within each SPDIF L/R

subframe) to be controlled by the V bit (D15) in Register 0x3A (SPDIF control register).

VFORCE = 0 and V = 0; the validity bit is managed by the codec error detection logic.

VFORCE = 0 and V = 1; the validity bit is forced high, indicating the subframe data is invalid.

VFORCE = 1 and V = 0; the validity bit is forced low, indicating the subframe data is valid.

VFORCE = 1 and V = 1; the validity bit is forced high, indicating the subframe data is invalid.

Table 32. AC ’97 2.2 AMAP-Compliant Default SPDIF Slot Assignments

Codec ID

Function

SPSA = 00

SPSA = 01

SPSA = 10

SPSA = 11

00

2-Channel Primary w/SPDIF

3 and 4

7 and 8 (default)

6 and 9

10 and 11

00

4-Channel Primary w/SPDIF

3 and 4

7 and 8

6 and 9 (default)

10 and 11

00

6-Channel Primary w/SPDIF

3 and 4

7 and 8

6 and 9

10 and 11 (default)

01

+2-Channel Secondary w/SPDIF

3 and 4

7 and 8

6 and 9 (default)

01

+4-Channel Secondary w/SPDIF

3 and 4

7 and 8

6 and 9

10 and 11 (default)

10

+2-Channel Secondary w/SPDIF

3 and 4

7 and 8

6 and 9 (default)

10

+4-Channel Secondary w/SPDIF

3 and 4

7 and 8

6 and 9

10 and 11 (default)

11

+2-Channel Secondary w/SPDIF

3 and 4

7 and 8

6 and 9

10 and 11 (default)

PCM FRONT DAC RATE REGISTER

Index 0x2C

Reg

No.

Name

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

Default

0x2C

PCM

Front

DAC

Rate

SRF15

SRF14

SRF13

SRF12

SRF11

SRF10

SRF9

SRF8

SRF7

SRF6

SRF5

SRF4

SRF3

SRF2

SRF1

SRF0

0xBB80

This read/write sample rate control register contains a 16-bit unsigned value, representing the rate of operation in Hz.

Table 33.

Bit

Mnemonic

Function

SRF [15:0]

Sample Rate

The sampling frequency range is from 7 kHz (0x1B58) to 48 kHz (0xBB80) in 1 Hz increments. If 0 is written to

VRA, the sample rate is reset to 48 kHz.

PCM ADC RATE REGISTER

Index 0x32

Reg

No.

Name

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

Default

0x32

PCM L/R

ADC

Rate

SRA15

SRA14

SRA13

SRA12

SRA11

SRA10

SRA9

SRA8

SRA7

SRA6

SRA5

SRA4

SRA3

SRA2

SRA1

SRA0

0xBB80

This read/write sample rate control register contains a 16-bit unsigned value, representing the rate of operation in Hz.

Table 34.

Bit

Mnemonic

Function

SRA

[15:0]

Sample Rate

The sampling frequency range is from 7 kHz (0x1B58) to 48 kHz (0xBB80) in 1 Hz increments. If 0 is written to

VRA, the sample rate is reset to 48 kHz.