AD1981B

Rev. C | Page 22 of 32

EXTENDED AUDIO ID REGISTER

Index 0x28

Reg No.

Name

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

Default

0x28

Ext’d Audio ID

IDC1

IDC0

X

X

REVC1

REVC0

AMAP

X

X

X

DSA1

DSA0

X

SPDIF

X

VRAS

0xX605

The extended audio ID register identifies which extended audio features are supported. A nonzero extended audio ID value indicates that one or more of the

extended audio features are supported.

All registers are not shown, and bits containing an X are assumed to be reserved.

Table 30.

Bit

Mnemonic

Function

VRAS

Variable Rate PCM Audio

Support (Read-Only)

This bit returns a 1 when Read To indicates that the variable rate PCM audio is supported.

SPDIF

SPDIF Support (Read-Only)

This bit returns a 1 when Read To indicates that the SPDIF transmitter is supported (IEC958).

This bit is also used to validate that the SPDIF transmitter output is enabled. The SPDIF bit can

be set high only if the SPDIF pin (Pin 48) is pulled down at power-up, enabling the codec

transmitter logic. If the SPDIF pin is floating or pulled high at power-up, the transmitter logic

is disabled; therefore, this bit returns a low, indicating that the SPDIF transmitter is not

available. This bit must always be read back to verify that the SPDIF transmitter is actually

enabled.

DSA [1:0]

DAC Slot Assignments

(Read/Write)

Reset default = 00.

00 DACs 1, 2 = 3 and 4.

01 DACs 1, 2 = 7 and 8.

10 DACs 1, 2 = 6 and 9.

11 Reserved.

AMAP

Slot DAC Mappings Based

on Codec ID (Read-Only)

This bit returns a 1 when read to indicate that slot/DAC mappings based on the codec ID are

supported.

REVC [1:0]

AC ’97 Revision Compliance

REVC [1:0] = 01 indicates that the codec is AC ’97 revision 2.2 compliant (read-only).

IDC [1:0]

Indicates Codec

Configuration (Read-Only)

00 = Primary.

01, 10, 11 = Secondary.

EXTENDED AUDIO STATUS AND CONTROL REGISTER

Index 0x2A

Reg

No.

Name

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

Default

0x2A

Ext’d Audio

Stat/Ctrl

VFORCE

X

X

X

X

SPCV

X

X

X

X

SPSA1

SPSA0

X

SPDIF

X

VRA

0x0000

All registers are not shown, and bits containing an X are assumed to be reserved.

The extended audio status and control register is a read/write register that provides status and control of the extended audio features.

Table 31.

Bit

Mnemonic

Function

VRA

Variable Rate Audio

(Read/Write)

VRA = 0 sets the fixed sample rate audio to 48 kHz (reset default).

VRA = 1 enables variable rate audio mode (enables sample rate registers and SLOTREQ

signaling).

SPDIF

SPDIF Transmitter

Subsystem Enable/Disable

Bit (Read/Write)

SPDIF = 1 enables the SPDIF transmitter.

SPDIF = 0 disables the SPDIF transmitter (default).

This bit is also used to validate that the SPDIF transmitter output is enabled. The SPDIF bit can

be set high only if the SPDIF pin (Pin 48) is pulled down at power-up, enabling the codec

transmitter logic. If the SPDIF pin is floating or pulled high at power-up, the transmitter logic is

disabled and this bit returns a low, indicating that the SPDIF transmitter is not available. This bit

must always be read back to verify that the SPDIF transmitter is enabled.

SPSA [1:0]

SPDIF Slot Assignment Bits

(Read/Write)

These bits control the SPDIF slot assignment and respective defaults, depending on the codec

ID configuration.