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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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AD1981BBSTZ датащи(PDF) 5 Page - Analog Devices |
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AD1981BBSTZ датащи(HTML) 5 Page - Analog Devices |
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5 / 32 page  AD1981B Rev. C | Page 5 of 32 Parameter Min Typ Max Unit High Level Output Voltage (VOH), IOH = 2 mA 0.9 × DVDD V Low Level Output Voltage (VOL), IOL = 2 mA 0.1 × DVDD V Input Leakage Current −10 +10 µA Output Leakage Current −10 +10 µA POWER SUPPLY Power Supply Range—Analog (AVDD) 4.5 5.5 V Power Supply Range—Digital (DVDD) 3.0 3.47 V Power Dissipation—5 V/3.3 V 400 mW Analog Supply Current—5 V (AVDD) 50 mA Digital Supply Current—3.3 V (DVDD) 46 mA Power Supply Rejection (100 mV p-p Signal @ 1 kHz)1 (At Both Analog and Digital Supply Pins, Both ADCs and DACs) 40 dB CLOCK SPECIFICATIONS1 Input Clock Frequency 24.576 MHz Recommended Clock Duty Cycle 40 50 60 % 1 Guaranteed but not tested. 2 Measurements reflect main ADC. POWER-DOWN STATES Values presented with VREFOUT not loaded. Table 3. Parameter Set Bits DVDD Typ AVDD Typ Unit Fully Active No Bits Value 42 51 mA ADC PR0 36 45 mA DAC PR1 29 35 mA ADC + DAC PR1, PR0 12 28 mA Mixer PR2 42 24 mA ADC + Mixer PR2, PR0 36 18 mA DAC + Mixer PR2, PR1 29 9 mA ADC + DAC + Mixer PR2, PR1, PR0 12 1.5 mA Standby PR5, PR4, PR3, PR2, PR1, PR0 0 0 mA Headphone Standby PR6 42 44 mA TIMING PARAMETERS Guaranteed over operating temperature range. Table 4. Parameter Symbol Min Typ Max Unit RESET Active Low Pulse Width tRST_LOW 1.0 ms RESET Inactive to BIT_CLK Start-Up Delay tRST2CLK 162.8 ns SYNC Active High Pulse Width tSYNC_HIGH 1.3 ms SYNC Low Pulse Width tSYNC_LOW 19.5 µs SYNC Inactive to BIT_CLK Start-Up Delay tSYNC2CLK 162.8 ns BIT_CLK Frequency 12.288 MHz BIT_CLK Frequency Accuracy ±1 ppm BIT_CLK Period tCLK_PERIOD 81.4 ns BIT_CLK Output Jitter1, ,2 3 750 2000 ps BIT_CLK High Pulse Width tCLK_HIGH 32.56 42 48.84 ns |
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