HT45F4M datasheet(14/138 Pages) HOLTEK

14 / 138 page

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HT45F4M

Lithium Battery Backup Power ASSP MCU

HT45F4M

Lithium Battery Backup Power ASSP MCU

System Architecture

Akeyfactorinthehigh-performancefeaturesoftheHoltekrangeofmicrocontrollersisattributed

totheirinternalsystemarchitecture.Thedevicetakesadvantageoftheusualfeaturesfoundwithin

RISCmicrocontrollersprovidingincreasedspeedofoperationandenhancedperformance.The

pipeliningschemeisimplementedinsuchawaythatinstructionfetchingandinstructionexecution

areoverlapped,henceinstructionsareeffectivelyexecutedinonecycle,withtheexceptionofbranch

orcallinstructions.An8-bitwideALUisusedinpracticallyallinstructionsetoperations,which

carriesoutarithmeticoperations,logicoperations,rotation,increment,decrement,branchdecisions,

etc.TheinternaldatapathissimplifiedbymovingdatathroughtheAccumulatorandtheALU.

CertaininternalregistersareimplementedintheDataMemoryandcanbedirectlyorindirectly

addressed.Thesimpleaddressingmethodsoftheseregistersalongwithadditionalarchitectural

featuresensurethataminimumofexternalcomponentsisrequiredtoprovideafunctionalI/Oand

A/Dcontrolsystemwithmaximumreliabilityandflexibility.Thismakesthedevicesuitableforlow-

cost,high-volumeproductionforcontrollerapplications.

Clocking and Pipelining

Themainsystemclock,derivedfromeitheranHIRCorLIRCoscillatorissubdividedintofour

internallygeneratednon-overlappingclocks,T1~T4.TheProgramCounterisincrementedatthe

beginningoftheT1clockduringwhichtimeanewinstructionisfetched.TheremainingT2~T4

clockscarryoutthedecodingandexecutionfunctions.Inthisway,oneT1~T4clockcycleforms

oneinstructioncycle.Althoughthefetchingandexecutionofinstructionstakesplaceinconsecutive

instructioncycles,thepipeliningstructureofthemicrocontrollerensuresthatinstructionsare

effectivelyexecutedinoneinstructioncycle.Theexceptiontothisareinstructionswherethe

contentsoftheProgramCounterarechanged,suchassubroutinecallsorjumps,inwhichcasethe

instructionwilltakeonemoreinstructioncycletoexecute.

Fe tc h In s t. (P C)

Ex ec ut e In s t. ( PC -1 )

Fe tc h In st . (P C+ 1)

Ex ec ut e In s t. ( PC )

Fe tc h In st . (P C+ 2)

Ex ec ut e In s t. ( PC +1 )

PC +1

PC +2

f SY S

(S ys te m Cl o ck)

Ph as e Cl o ck T1

Pr ogr am C ount er

Ph as e Cl o ck T2

Ph as e Cl o ck T3

Ph as e Cl o ck T4

Pi pe li ni ng

System Clock and Pipelining

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