HT45F4M datasheet(91/138 Pages) HOLTEK

91 / 138 page

Rev. 1.10

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Rev. 1.10

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HT45F4M

Lithium Battery Backup Power ASSP MCU

HT45F4M

Lithium Battery Backup Power ASSP MCU

A/D Operation

TheSTARTbitintheADCR0registerisusedtostartandresettheA/Dconverter.Whenthe

microcontrollersetsthisbitfromlowtohighandthenlowagain,ananalogtodigitalconversion

cyclewillbeinitiated.WhentheSTARTbitisbroughtfromlowtohighbutnotlowagain,the

EOCBbitintheADCR0registerwillbesethighandtheanalogtodigitalconverterwillbereset.

ItistheSTARTbitthatisusedtocontroltheoverallstartoperationoftheinternalanalogtodigital

converter.

TheEOCBbitintheADCR0registerisusedtoindicatewhentheanalogtodigitalconversion

processiscomplete.Thisbitwillbeautomaticallysetto“0”bythemicrocontrolleraftera

conversioncyclehasended.Inaddition,thecorrespondingA/Dinterruptrequestflagwillbeset

intheinterruptcontrolregister,andiftheinterruptsareenabled,anappropriateinternalinterrupt

signalwillbegenerated.ThisA/Dinternalinterruptsignalwilldirecttheprogramflowtothe

associatedA/Dinternalinterruptaddressforprocessing.IftheA/Dinternalinterruptisdisabled,

themicrocontrollercanbeusedtopolltheEOCBbitintheADCR0registertocheckwhetherithas

beenclearedasanalternativemethodofdetectingtheendofanA/Dconversioncycle.

TheclocksourcefortheA/Dconverter,whichoriginatesfromthesystemclockfSYS,canbechosen

tobeeitherfSYSorasubdividedversionoffSYS.Thedivisionratiovalueisdeterminedbythe

ADCK2~ADCK0bitsintheADCR1register.

AlthoughtheA/DclocksourceisdeterminedbythesystemclockfSYS,andbybitsADCK2~ADCK0,

therearesomelimitationsontheA/Dclocksourcespeedrangethatcanbeselected.Asthe

recommendedrangeofpermissibleA/Dclockperiod,tADCK,isfrom0.5µsto10µs,caremustbe

takenforselectedsystemclockfrequencies.Forexample,ifthesystemclockoperatesatafrequency

of4MHz,theADCK2~ADCK0bitsshouldnotbesetto000Bor110B.DoingsowillgiveA/D

clockperiodsthatarelessthantheminimumA/DclockperiodorgreaterthanthemaximumA/D

clockperiodwhichmayresultininaccurateA/Dconversionvalues.

Refertothefollowingtableforexamples,wherevaluesmarkedwithanasterisk*showwhere,

dependinguponthedevice,specialcaremustbetaken,asthevaluesmaybeoutoftherecommended

A/Dclockperiodrange.

fSYS

A/D Clock Period (tADCK)

ADCK2,

ADCK1,

ADCK0

=000

(fSYS)

ADCK2,

ADCK1,

ADCK0

=001

(fSYS/2)

ADCK2,

ADCK1,

ADCK0

=010

(fSYS/4)

ADCK2,

ADCK1,

ADCK0

=011

(fSYS/8)

ADCK2,

ADCK1,

ADCK0

=100

(fSYS/16)

ADCK2,

ADCK1,

ADCK0

=101

(fSYS/32)

ADCK2,

ADCK1,

ADCK0

=110

(fSYS/64)

ADCK2,

ADCK1,

ADCK0

=111

1MHz

1μs

�μs

4μs

8μs

16μs*

��μs*

64μs*

Undefined

�MHz

�00ns

1μs

�μs

4μs

8μs

16μs*

��μs*

Undefined

4MHz

��0ns*

�00ns

1μs

�μs

4μs

8μs

16μs*

Undefined

8MHz

1��ns*

��0ns*

�00ns

1μs

�μs

4μs

8μs

Undefined

1�MHz

8�ns*

167ns*

��ns*

667ns

1.��μs

�.67μs

�.��μs

Undefined

16MHz

6�.�ns*

1��ns*

��0ns*

�00ns

1μs

�μs

4μs

Undefined

�0MHz

�0ns*

100ns*

�00ns*

400ns*

800ns

1.6μs

�.�μs

Undefined

A/D Clock Period Examples

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