ADF4151 datasheet(23/28 Pages) AD

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Data Sheet

ADF4151

Rev. B | Page 23 of 28

Reference Spurs

Reference spurs are generally not a problem in fractional-N

synthesizers because the reference offset is far outside the loop

bandwidth. However, any reference feedthrough mechanism

that bypasses the loop can cause a problem. Feedthrough of low

levels of on-chip reference switching noise, through the RFIN

pin back to the VCO, can result in reference spur levels as high

as −90 dBc. PCB layout must ensure adequate isolation between

VCO traces and the input reference to avoid a possible

feedthrough path on the board.

SPUR CONSISTENCY AND FRACTIONAL SPUR

OPTIMIZATION

With dither off, the fractional spur pattern due to the quanti-

zation noise of the SDM also depends on the particular phase

word with which the modulator is seeded.

The phase word can be varied to optimize the fractional and

subfractional spur levels on any particular frequency. Thus, a

look-up table of phase values corresponding to each frequency

can be constructed for use when programming the ADF4151.

If a look-up table is not used, keep the phase word at a constant

value to ensure consistent spur levels on any particular frequency.

PHASE RESYNC

The output of a fractional-N PLL can settle to any one of the

MOD phase offsets with respect to the input reference, where

MOD is the fractional modulus. The phase resync feature in the

ADF4151 produces a consistent output phase offset with respect

to the input reference. This is necessary in applications where the

output phase and frequency are important, such as digital beam

forming. See the Phase Programmability section for how to

program a specific RF output phase when using phase resync.

Phase resync is enabled by setting Bit DB16, Bit DB15 in

timer generates sync signals at intervals of tSYNC given by the

following formula:

tSYNC = CLK_DIV_VALUE × MOD × tPFD

where:

CLK_DIV_VALUE is the decimal value programmed in

Bits[DB14:DB3] of Register 3 and can be any integer in the

range of 1 to 4095.

MOD is the modulus value programmed in Bits[DB14:DB3] of

tPFD is the PFD reference period.

When a new frequency is programmed, the second sync pulse

after the LE rising edge is used to resynchronize the output

phase to the reference. The tSYNC time must be programmed to

a value that is at least as long as the worst-case lock time. This

guarantees that the phase resync occurs after the last cycle slip

in the PLL settling transient.

In the example shown in Figure 28, the PFD reference is

25 MHz and MOD is 125 for a 200 kHz channel spacing. tSYNC

is set to 400 µs by programming the clock divider value,

CLK_DIV_VALUE, to 80.

PHASE

FREQUENCY

SYNC

(INTERNAL)

–100

100

200

1000

300

400

500

600

700

800

900

TIME (µs)

PLL SETTLES TO

CORRECT PHASE

AFTER RESYNC

tSYNC

LAST CYCLE SLIP

PLL SETTLES TO

INCORRECT PHASE

Figure 28. Phase Resync Example

Phase Programmability

The phase word in Register 1 controls the RF output phase. As

this word is swept from 0 to MOD, the RF output phase sweeps

over a 360° range in steps of 360°/MOD.

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