ADF4151

Data Sheet

Rev. B | Page 2 of 28

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications....................................................................................... 1

General Description ......................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Timing Characteristics ................................................................ 5

Absolute Maximum Ratings............................................................ 6

Transistor Count........................................................................... 6

ESD Caution.................................................................................. 6

Pin Configuration and Function Descriptions............................. 7

Typical Performance Characteristics ............................................. 9

Circuit Description......................................................................... 11

Reference Input Section............................................................. 11

RF N Divider............................................................................... 11

INT, FRAC, MOD, and R Counter Relationship.................... 11

INT N Mode................................................................................ 11

R Counter .................................................................................... 11

Phase Frequency Detector (PFD) and Charge Pump............ 11

MUXOUT and Lock Detect...................................................... 12

Input Shift Registers................................................................... 12

Program Modes .......................................................................... 12

Register Maps.............................................................................. 13

Register 0 ..................................................................................... 17

Register 1 ..................................................................................... 17

Register 2 ..................................................................................... 17

Register 3 ..................................................................................... 19

Register 4 ..................................................................................... 19

Register 5 ..................................................................................... 19

Initialization Sequence .............................................................. 19

RF Synthesizer—A Worked Example ...................................... 20

Modulus....................................................................................... 20

Reference Doubler and Reference Divider ............................. 20

12-Bit Programmable Modulus................................................ 20

Cycle Slip Reduction for Faster Lock Times........................... 21

Spurious Optimization and Fast lock ...................................... 21

Fast Lock Timer and Register Sequences................................ 21

Fast Lock—An Example............................................................ 22

Fast Lock—Loop Filter Topology............................................. 22

Spur Mechanisms ....................................................................... 22

Spur Consistency and Fractional Spur Optimization ........... 23

Phase Resync............................................................................... 23

Applications Information .............................................................. 24

Direct Conversion Modulator .................................................. 24

Interfacing ................................................................................... 25

PCB Design Guidelines for Chip Scale Package .................... 25

Outline Dimensions....................................................................... 26

Ordering Guide .......................................................................... 26

REVISION HISTORY

12/11—Rev. A to Rev. B

Changes to Normalized 1/f Noise Parameter, Table 1 ................. 4

11/11—Rev. 0 to Rev. A

Changes to Figure 28...................................................................... 23

10/11—Revision 0: Initial Version