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Data Sheet

ADF4151

Rev. B | Page 11 of 28

CIRCUIT DESCRIPTION

REFERENCE INPUT SECTION

The reference input stage is shown in Figure 14. SW1 and SW2

are normally closed switches. SW3 is normally open. When

power-down is initiated, SW3 is closed and SW1 and SW2 are

opened. This ensures that there is no loading of the REFIN pin

on power-down.

BUFFER

TO R COUNTER

REFIN

100k

Ω

SW2

SW3

SW1

POWER-DOWN

CONTROL

Figure 14. Reference Input Stage

RF N DIVIDER

The RF N divider allows a division ratio in the PLL feedback

path. Division ratio is determined by the INT, FRAC, and MOD

values, which build up this divider.

INT, FRAC, MOD, AND R COUNTER RELATIONSHIP

The INT, FRAC, and MOD values, in conjunction with the R

counter, make it possible to generate output frequencies that

are spaced by fractions of the PFD frequency. See the RF

Synthesizer—A Worked Example section for more

information. The RF VCO frequency (RFOUT) equation is

RFOUT = fPFD × (INT + (FRAC/MOD))

(1)

where:

RFOUT is the output frequency of the external voltage controlled

oscillator (VCO).

INT is the preset divide ratio of the binary 16-bit counter

(23 to 32,767 for 4/5 prescaler, 75 to 65,535 for 8/9 prescaler).

FRAC is the numerator of the fractional division (0 to MOD − 1).

MOD is the preset fractional modulus (2 to 4095 for low noise

mode, 50 to 4095 for low spur mode).

fPFD = REFIN × [(1 + D)/(R × (1 + T))]

(2)

where:

REFIN is the reference input frequency.

D is the REFIN doubler bit.

R is the preset divide ratio of the binary 10–bit programmable

reference counter (1 to 1023).

T is the REFIN divide-by-2 bit (0 or 1).

THIRD-ORDER

FRACTIONAL

INTERPOLATOR

FRAC

VALUE

MOD

REG

INT

REG

RF N DIVIDER

N = INT + FRAC/MOD

FROM

VCO OUTPUT/

OUTPUT DIVIDERS

TO PFD

N COUNTER

Figure 15. RF INT Divider

INT N MODE

If the FRAC = 0 and DB8 in Register 2 (LDF) is set to 1, the

synthesizer operates in integer-N mode. The DB8 in Register 2

(LDF) should be set to 1 to get integer-N digital lock detect.

Additionally, lower phase noise is possible if the antibacklash

pulse width is reduced to 3 ns. This mode is not valid for

fractional-N applications.

R COUNTER

The 10-bit R counter allows the input reference frequency

(REFIN) to be divided down to produce the reference clock

to the PFD. Division ratios from 1 to 1023 are allowed.

PHASE FREQUENCY DETECTOR (PFD) AND

CHARGE PUMP

The phase frequency detector (PFD) takes inputs from the R

counter and N counter and produces an output proportional to

the phase and frequency difference between them. Figure 16 is

a simplified schematic of the phase frequency detector. The PFD

includes a programmable delay element that sets the width of

the antibacklash pulse, which can be either 6 ns (default, for

fractional-N applications) or 3 ns (for integer-N mode). This

pulse ensures that there is no dead zone in the PFD transfer

function and gives a consistent reference spur level.

CLR2

DOWN

HIGH

–IN

+IN

CHARGE

PUMP

DELAY

CLR1

Figure 16. PFD Simplified Schematic

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