ADF4151 datasheet(21/28 Pages) AD

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Data Sheet

ADF4151

Rev. B | Page 21 of 28

A 13 MHz reference signal can be fed directly to the PFD, and

the modulus can be programmed to 520 when in PDC mode

(13 MHz/520 = 25 kHz).

The modulus needs to be reprogrammed to 65 for GSM 1800

operation (13 MHz/65 = 200 kHz).

It is important that the PFD frequency remain constant (13 MHz).

This allows the user to design one loop filter for both setups

without running into stability issues. It is important to remem-

ber that the ratio of the RF frequency to the PFD frequency

principally affects the loop filter design, not the actual channel

spacing.

CYCLE SLIP REDUCTION FOR FASTER LOCK TIMES

As outlined in the Low Noise and Spur Mode section, the

ADF4151 contains a number of features that allow optimization

for noise performance. However, in fast locking applications,

the loop bandwidth generally needs to be wide, and, therefore,

the filter does not provide much attenuation of the spurs. If

the cycle slip reduction feature is enabled, the narrow-loop

bandwidth is maintained for spur attenuation but faster lock

times are still possible.

Cycle Slips

Cycle slips occur in integer-N/fractional-N synthesizers when

the loop bandwidth is narrow compared to the PFD frequency.

The phase error at the PFD inputs accumulates too fast for the

PLL to correct, and the charge pump temporarily pumps in the

wrong direction. This slows down the lock time dramatically.

The ADF4151 contains a cycle slip reduction feature that

extends the linear range of the PFD, allowing faster lock

times without modifications to the loop filter circuitry.

When the circuitry detects that a cycle slip is about to occur,

it turns on an extra charge pump current cell. This outputs a

constant current to the loop filter or removes a constant

current from the loop filter (depending on whether the VCO

tuning voltage needs to increase or decrease to acquire the

new frequency). The effect is that the linear range of the PFD

is increased. Loop stability is maintained because the current

is constant and is not a pulsed current.

If the phase error increases again to a point where another cycle

slip is likely, the ADF4151 turns on another charge pump cell.

This continues until the ADF4151 detects that the VCO

frequency has gone past the desired frequency. The extra charge

pump cells are turned off one by one until all the extra charge

pump cells have been disabled and the frequency is settled with

the original loop filter bandwidth.

Up to seven extra charge pump cells can be turned on. In most

applications, it is enough to eliminate cycle slips altogether,

giving much faster lock times.

Setting Bit DB18 in the Register 3 to 1 enables cycle slip

reduction. Note that the PFD requires a 45% to 55% duty

cycle for CSR to operate correctly.

SPURIOUS OPTIMIZATION AND FAST LOCK

Narrow-loop bandwidths can filter unwanted spurious signals,

but these usually have a long lock time. A wider loop bandwidth

achieves faster lock times, but a wider loop bandwidth may lead

to increased spurious signals inside the loop bandwidth.

The fast lock feature can achieve the same fast lock time as the

wider bandwidth, but with the advantage of a narrow final loop

bandwidth to keep spurs low.

FAST LOCK TIMER AND REGISTER SEQUENCES

If the fast lock mode is used, a timer value must be loaded into

the PLL to determine the duration of the wide bandwidth mode.

When Bits[DB16:DB15] in Register 3 are set to 0, 1 (fast

lock enable), the timer value is loaded by the 12-bit clock

divider value. The following sequence must be programmed

to use fast lock:

1. Initialization sequence (see the Initialization Sequence

section); occurs only once after powering up the part.

2. Load Register 3 by setting Bits[DB16:DB15] to 0, 1 and

the chosen fast lock timer value, Bits[DB14:DB3]. Note that

the length of time the PLL remains in wide bandwidth is

equal to the fast lock timer/fPFD.

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