ADF4151 datasheet(17/28 Pages) AD

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Data Sheet

ADF4151

Rev. B | Page 17 of 28

Control Bits

With Bits[C3:C1] set to 0, 0, 0, Register 0 is programmed.

Figure 19 shows the input data format for programming this

16-Bit Integer Value (INT)

These 16 bits set the INT value, which determines the integer

part of the feedback division factor. They are used in Equation 1

(see the INT, FRAC, MOD, and R Counter Relationship

section). All integer values from 23 to 32,767 are allowed for 4/5

prescaler. For 8/9 prescaler, the minimum integer value is 75, and

the maximum value is 65,535.

12-Bit Fractional Value (FRAC)

The 12 FRAC bits set the numerator of the fraction that is input

to the Σ-Δ modulator. This, along with INT, specifies the new

frequency channel that the synthesizer locks to, as shown in the

RF Synthesizer—A Worked Example section. FRAC values from

0 to MOD − 1 cover channels over a frequency range equal to

the PFD reference frequency.

Control Bits

With Bits[C3:C1] set to 0, 0, 1, Register 1 is programmed.

Figure 20 shows the input data format for programming

this register.

Phase Adjust

The phase adjust bit, enabled by programming a 1 to DB28,

permits adjustments to the output phase of a given output

frequency. If enabled, it does not perform a phase resync

function on updating R0. If set to 0, the phase resync (if

enabled in R3, Bits[DB16:DB15]) occurs on every update

of R0.

Prescaler Value

The dual modulus prescaler (P/P + 1), along with the INT,

FRAC, and MOD counters, determines the overall division

ratio from the VCO output to the PFD input.

Operating at CML levels, it takes the clock from the VCO

output and divides it down for the counters. It is based on a

synchronous 4/5 core. When set to 4/5, the maximum RF

frequency allowed is 3 GHz. Therefore, when operating the

ADF4151 above 3 GHz, this must be set to 8/9. The prescaler

limits the INT value, where:

P = 4/5, NMIN = 23

P = 8/9, NMIN = 75

In the ADF4151, PR1 in Register 1 sets the prescaler values.

12-Bit Phase Value (PHASE)

These bits control what is loaded as the phase word. The word

must be less than the MOD value programmed in Register 1.

The word is used to program the RF output phase from 0° to

360° with a resolution of 360°/MOD. See the Phase Resync

section for more information. In most applications, the phase

relationship between the RF signal and the reference is not

important. In such applications, the phase value can be used to

optimize the fractional and subfractional spur levels. See the

Spur Consistency and Fractional Spur Optimization section for

more information.

If neither the phase resync nor the spurious optimization

functions are being used, it is recommended that the phase

word be set to 1.

12-Bit Modulus Value (MOD)

This programmable register sets the fractional modulus. This

is the ratio of the PFD frequency to the channel step resolution

on the RF output. See the RF Synthesizer—A Worked Example

section for more information.

Control Bits

With Bits[C3:C1] set to 0, 1, 0, Register 2 is programmed.

Figure 21 shows the input data format for programming

this register.

Low Noise and Spur Modes

The noise modes on the ADF4151 are controlled by DB30 and

DB29 in Register 2 (see Figure 21). The noise modes allow the

user to optimize a design either for improved spurious perfor-

mance or for improved phase noise performance.

When the lowest spur setting is chosen, dither is enabled. This

randomizes the fractional quantization noise so it resembles

white noise rather than spurious noise. As a result, the part is

optimized for improved spurious performance. This operation

would normally be used when the PLL closed-loop bandwidth

is wide, for fast locking applications. (Wide-loop bandwidth is

seen as a loop bandwidth greater than 1/10 of the RFOUT channel

step resolution (fRES)). A wide loop filter does not attenuate the

spurs to the same level as a narrow-loop bandwidth.

For best noise performance, use the lowest noise setting option.

As well as disabling the dither, it also ensures that the charge

pump is operating in an optimum region for noise performance.

This setting is extremely useful where a narrow-loop filter

bandwidth is available. The synthesizer ensures extremely low

noise, and the filter attenuates the spurs. The typical performance

characteristics give the user an idea of the trade-off in a typical

W-CDMA setup for the different noise and spur settings.

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