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ADF4151 датащи(PDF) 13 Page - Analog Devices

номер детали ADF4151
подробное описание детали  Fractional-N/Integer-N PLL Synthesizer
PDF  28 Pages
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производитель  AD [Analog Devices]
домашняя страница  http://www.analog.com
Logo AD - Analog Devices

ADF4151 датащи(HTML) 13 Page - Analog Devices

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Data Sheet
ADF4151
Rev. B | Page 13 of 28
REGISTER MAPS
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3
DB2
DB1
DB0
0
N16
N15
N14
N13
N12
N11
N10
N9
16-BIT INTEGER VALUE (INT)
12-BIT FRACTIONAL VALUE (FRAC)
CONTROL
BITS
N8
N7
N6
N5
N4
N3
N2
N1
F12
F11
F10
F9
F8
F7
F6
F5
F4
F3
F2
F1
C3(0) C2(0) C1(0)
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4
DB3
DB2
DB1
DB0
0
0
0
PH1
PR1
P12
P11
P10
P9
12-BIT PHASE VALUE (PHASE)
12-BIT MODULUS VALUE (MOD)
CONTROL
BITS
P8
P7
P6
P5
P4
P3
P2
P1
M12
M11
M10
M9
M8
M7
M6
M5
M4
M3
M2
M1
C3(0) C2(0) C1(1)
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4
DB3
DB2
DB1
DB0
0
L2
L1
M3
M2
M1
RD2
RD1
R10
R9
R8
R7
R6
R5
R4
R3
R2
R1
0
CP4
CP3
CP2
CP1
U6
U5
U4
U3
U2
U1
C3(0) C2(1) C1(0)
CHARGE
PUMP
CURRENT
SETTING
10-BIT R COUNTER
CONTROL
BITS
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4
DB3
DB2
DB1
DB0
0
0
0
0
0
0
0
0
0
F3
F2
0
0
F1
0
C2
C1
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
C3(0) C2(1) C1(1)
CONTROL
BITS
12-BIT CLOCK DIVIDER VALUE
CLK
DIV
MODE
DBR 1
1 DBR = DOUBLE BUFFERED REGISTER—BUFFERED BY THE WRITE TO REGISTER 0.
RESERVED
RESERVED
REGISTER 4
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4
DB3
DB2
DB1
DB0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
C3(1) C2(0) C1(0)
CONTROL
BITS
RESERVED
LD PIN
MODE
REGISTER 0
REGISTER 1
REGISTER 2
REGISTER 3
REGISTER 5
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4
DB3
DB2
DB1
DB0
0
0
0
0
0
0
0
0
D15
D14
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
C3(1) C2(0) C1(1)
CONTROL
BITS
RESERVED
RESERVED
RESERVED
DBR1
DBR1
DBR1
LOW
NOISE AND
LOW SPUR
MODES
MUXOUT
Figure 18. Register Summary



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