ADF4151 datasheet(18/28 Pages) AD

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ADF4151

Data Sheet

Rev. B | Page 18 of 28

MUXOUT

The on-chip multiplexer is controlled by Bits[DB28:DB26] (see

Figure 21).

Reference Doubler

Setting DB25 to 0 feeds the REFIN signal directly to the 10-bit

R counter, disabling the doubler. Setting this bit to 1 multiplies

the REFIN frequency by a factor of 2 before feeding into the

10-bit R counter. When the doubler is disabled, the REFIN

falling edge is the active edge at the PFD input to the fractional

synthesizer. When the doubler is enabled, both the rising and

falling edges of REFIN become active edges at the PFD input.

When the doubler is enabled and the lowest spur mode is

chosen, the in-band phase noise performance is sensitive to the

REFIN duty cycle. The phase noise degradation can be as much

as 5 dB for the REFIN duty cycles outside a 45% to 55% range.

The phase noise is insensitive to the REFIN duty cycle in the

lowest noise mode. The phase noise is insensitive to the REFIN

duty cycle when the doubler is disabled.

When the doubler is enabled, the maximum allowable REFIN

frequency is 30 MHz.

RDIV2

Setting the DB24 bit to 1 inserts a divide-by-2 toggle flip-flop

between the R counter and PFD, which extends the maximum

REFIN input rate. This function allows a 50% duty cycle signal

to appear at the PFD input, which is necessary for cycle slip

reduction.

10-Bit R Counter

The 10-bit R counter allows the input reference frequency

(REFIN) to be divided down to produce the reference clock to

the PFD. Division ratios from 1 to 1023 are allowed.

Current Setting

Bits[DB12:DB9] set the charge pump current setting. This

should be set to the charge pump current that the loop filter

is designed with (see Figure 21).

LDF

Setting DB8 to 1 enables integer-N digital lock detect, when

the FRAC part of the divider is zero; setting DB8 to 0 enables

fractional-N digital lock detect.

Lock Detect Precision (LDP)

When DB7 is set to 0, the fractional-N digital lock detect is

activated. In this case after setting DB7 to 0, 40 consecutive PFD

cycles of 10 ns must occur before digital lock detect is set. When

DB7 is programmed to 1, 40 consecutive reference cycles of 6 ns

must occur before digital lock detect goes high. Setting DB8

(LDF) to 1 causes the activation of the integer-N digital lock

detect. In this case, after setting DB7 (LDP) to 0, five

consecutive cycles of 10 ns must occur before digital lock detect

is set. When DB7 is set to 1, five consecutive cycles of 6 ns must

occur. Recommended settings of both the LDP and LDF bits are

shown in Table 6.

Table 6. Recommended LDF/LDP Bit Settings

Mode

DB8

(LDF)

DB7

(LDP)

Integer-N

Fractional-N Low Noise Mode

Fractional-N Low Spur Mode

Phase Detector Polarity

DB6 sets the phase detector polarity. When a passive loop filter

or noninverting active loop filter is used, set this bit to 1. If an

active filter with an inverting characteristic is used, this bit

should be set to 0.

Power-Down (PD)

DB5 provides the programmable power-down mode. Setting this

bit to 1 performs a power-down. Setting this bit to 0 returns the

synthesizer to normal operation. When in software power-down

mode, the part retains all information in its registers. Only if the

supply voltages are removed are the register contents lost.

When a power-down is activated, the following events occur:

•

The synthesizer counters are forced to their load state

conditions.

•

The charge pump is forced into three-state mode.

•

The digital lock detect circuitry is reset.

•

The RFOUT buffers are disabled.

•

The input register remains active and capable of loading

and latching data.

Charge Pump (CP) Three-State

DB4 puts the charge pump into three-state mode when

programmed to 1. It should be set to 0 for normal operation.

Counter Reset

DB3 is the R counter and N counter reset bit for the ADF4151.

When this bit is 1, the RF synthesizer N counter and R counter

are held in reset. For normal operation, this bit should be set to 0.

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