ADF4151 datasheet(19/28 Pages) AD

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Data Sheet

ADF4151

Rev. B | Page 19 of 28

Control Bits

With Bits[C3:C1] set to 0, 1, 1, Register 3 is programmed.

Figure 22 shows the input data format for programming

this register.

Antibacklash Pulse Width

Setting DB22 to 0 sets the PFD antibacklash pulse width to 6 ns.

This is the recommended mode for fractional-N use. By setting

this bit to 1, the 3 ns pulse width is used and results in a phase

noise and spur improvement in integer-N operation. For

fractional-N mode it is not recommended to use this smaller

setting.

Charge Cancellation Mode Pulse Width

Setting DB21 to 1 enables charge pump charge cancellation.

This has the effect of reducing PFD spurs in integer-N mode.

In fractional-N mode, this bit should not be used. This results

in a phase noise and fractional spur improvement.

Cycle Slip Reduction (CSR) Enable

Setting DB18 to 1 enables cycle slip reduction. This is a method

for improving lock times. Note that the signal at the phase fre-

quency detector (PFD) must have a 50% duty cycle for cycle slip

reduction to work. The charge pump current setting must also

be set to a minimum. See the Cycle Slip Reduction for Faster

Lock Times section for more information.

Clock Divider Mode

Bits[DB16:DB15] must be set to 1, 0 to activate phase resync or

0, 1 to activate fast lock. Setting Bits[DB16:DB15] to 0, 0

disables the clock divider. See Figure 22.

12-Bit Clock Divider Value

The 12-bit clock divider value sets the timeout counter for

activation of phase resync. See the Phase Resync section for

more information. It also sets the timeout counter for fast lock.

See the Fast Lock Timer and Register Sequences section for

more information.

Control Bits

With Bits[C3: C1] set to 1, 0, 0, Register 4 is programmed.

Figure 23 shows the input data format for programming this

This register is reserved and has to be programmed with the

values as shown in Figure 23. Bits[DB31:DB24] and [DB22:DB3]

must be programmed to 0, while Bit DB23 must be set to 1.

Control Bits

With Bits[C3:C1] set to 1, 0, 1, Register 5 is programmed.

Figure 24 shows the input data form for programming this

Lock Detect PIN Operation

Bits[DB23:DB22] set the operation of the lock detect pin (see

Figure 24).

INITIALIZATION SEQUENCE

The following sequence of registers is the correct sequence for

initial power up of the ADF4151 after the correct application

of voltages to the supply pins:

1. Register 5

2. Register 4

3. Register 3

4. Register 2

5. Register 1

6. Register 0

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