Data Sheet

ADF4151

Rev. B | Page 7 of 28

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

1

CLK

2

DATA

3

LE

4

CE

5

SW

6

7

24

23

NC

22

21

20

19

18

17

8

ADF4151

TOP VIEW

(Not to Scale)

PIN 1

INDICATOR

NC

NC

NC

NOTES

1. NC = NO CONNECT. DO NOT CONNECT TO THIS PIN.

2. THE LFCSP HAS AN EXPOSED PADDLE THAT MUST

BE CONNECTED TO GND.

Figure 3. Pin Configuration

Table 4. Pin Function Descriptions

Pin No.

Mnemonic

Description

1

CLK

Serial Clock Input. Data is clocked into the 32-bit shift register on the CLK rising edge. This input is a high

impedance CMOS input.

2

DATA

Serial Data Input. The serial data is loaded, MSB first, with the three LSBs as the control bits. This input is a high

impedance CMOS input.

3

LE

Load Enable, CMOS Input. When LE goes high, the data stored in the shift register is loaded into the register

that is selected by the three LSBs.

4

CE

Chip Enable. A logic low on this pin powers down the device and puts the charge pump into three-state

mode. Taking the pin high powers up the device depending on the status of the power-down bits.

5

SW

Fast Lock Switch. Make a connection to this pin from the loop filter when using the fast lock mode.

6

can be set to 5.5 V and used to drive a VCO with a tuning range of up to 5.5 V.

7

8

9, 11, 18,

21

10

Analog Power Supply. This pin ranges from 3.0 V to 3.6 V. Decoupling capacitors to the analog ground plane

12, 13, 19,

20, 23, 24

NC

No connect. Do not connect to this pin.

14

Input to the RF Input. This small signal input is ac-coupled to the external VCO.

15

Complementary Input to the RF Input. This pin must be decoupled to the ground plane with a small bypass

capacitor, typically 100 pF.

16, 17

Analog Power Supply. This pin ranges from 3.0 V to 3.6 V. Decoupling capacitors to the analog ground plane