LPC4350 datasheet(105/145 Pages) NXP

105 / 145 page

LPC4350_30_20_10

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Objective data sheet

Rev. 2.1 — 23 September 2011

105 of 145

NXP Semiconductors

LPC4350/30/20/10

32-bit ARM Cortex-M4/M0 microcontroller

[1]

Parameters are valid over operating temperature range unless otherwise specified.

[2]

tHD;DAT is the data hold time that is measured from the falling edge of SCL; applies to data in transmission and the acknowledge.

[3]

A device must internally provide a hold time of at least 300 ns for the SDA signal (with respect to the VIH(min) of the SCL signal) to

bridge the undefined region of the falling edge of SCL.

[4]

Cb = total capacitance of one bus line in pF. If mixed with Hs-mode devices, faster fall times are allowed.

[5]

The maximum tf for the SDA and SCL bus lines is specified at 300 ns. The maximum fall time for the SDA output stage tf is specified at

250 ns. This allows series protection resistors to be connected in between the SDA and the SCL pins and the SDA/SCL bus lines

without exceeding the maximum specified tf.

[6]

In Fast-mode Plus, fall time is specified the same for both output stage and bus timing. If series resistors are used, designers should

allow for this when considering bus timing.

[7]

The maximum tHD;DAT could be 3.45 s and 0.9 s for Standard-mode and Fast-mode but must be less than the maximum of tVD;DAT or

tVD;ACK by a transition time. This maximum must only be met if the device does not stretch the LOW period (tLOW) of the SCL signal. If

the clock stretches the SCL, the data must be valid by the set-up time before it releases the clock.

[8]

tSU;DAT is the data set-up time that is measured with respect to the rising edge of SCL; applies to data in transmission and the

acknowledge.

[9]

A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system but the requirement tSU;DAT = 250 ns must then be met.

This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the

LOW period of the SCL signal, it must output the next data bit to the SDA line tr(max) + tSU;DAT = 1000 + 250 = 1250 ns (according to the

Standard-mode I2C-bus specification) before the SCL line is released. Also the acknowledge timing must meet this set-up time.

tLOW

LOW period of the SCL clock

Standard-mode

4.7

s

Fast-mode

1.3

s

Fast-mode Plus

0.5

s

tHIGH

HIGH period of the SCL clock

Standard-mode

4.0

s

Fast-mode

0.6

s

Fast-mode Plus

0.26

s

tHD;DAT

data hold time

[2][3][7]

Standard-mode

s

Fast-mode

s

Fast-mode Plus

s

tSU;DAT

data set-up time

[8][9]

Standard-mode

250

Fast-mode

100

Fast-mode Plus

Table 13.

Dynamic characteristic: I2C-bus pins

Tamb = 40 C to +85 C.[1]

Symbol

Parameter

Conditions

Min

Max

Unit

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