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MPC8306EC датащи(PDF) 11 Page - Freescale Semiconductor, Inc |
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MPC8306EC датащи(HTML) 11 Page - Freescale Semiconductor, Inc |
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11 / 76 page ![]() MPC8306 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0 Freescale Semiconductor 11 Power Characteristics Table 6 shows the estimated typical I/O power dissipation for the device. Table 6. Typical I/O Power Dissipation Interface Parameter GVDD (1.8 V) OVDD (3.3 V) Unit Comments DDR I/O 65% utilization 1.8 V Rs = 20 Rt = 50 1 pair of clocks 266 MHz, 1 16 bits 0.141 — W — Local bus I/O load = 25 pF 1 pair of clocks 66 MHz, 26 bits —0.150 W 1 QUICC Engine block and other I/Os TDM serial, HDLC/TRAN serial, DUART, MII, RMII, Ethernet management, USB, SPI , Timer output FlexCAN eSDHC Note: 1. Typical IO power is based on a nominal voltage of VDD = 3.3V, ambient temperature, and the core running a Dhrystone benchmark application. The measurements were taken on the evaluation board using WC process silicon. |
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