поискавой системы для электроныых деталей
  Russian  ▼
ALLDATASHEETRU.COM

X  

Preview PDF HTML

MPC8306EC датащи(PDF) 63 Page - Freescale Semiconductor, Inc

номер детали MPC8306EC
подробное описание детали  PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications
PDF  76 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
производитель  FREESCALE [Freescale Semiconductor, Inc]
домашняя страница  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

MPC8306EC датащи(HTML) 63 Page - Freescale Semiconductor, Inc

Back Button MPC8306EC Datasheet HTML 59Page - Freescale Semiconductor, Inc MPC8306EC Datasheet HTML 60Page - Freescale Semiconductor, Inc MPC8306EC Datasheet HTML 61Page - Freescale Semiconductor, Inc MPC8306EC Datasheet HTML 62Page - Freescale Semiconductor, Inc MPC8306EC Datasheet HTML 63Page - Freescale Semiconductor, Inc MPC8306EC Datasheet HTML 64Page - Freescale Semiconductor, Inc MPC8306EC Datasheet HTML 65Page - Freescale Semiconductor, Inc MPC8306EC Datasheet HTML 66Page - Freescale Semiconductor, Inc MPC8306EC Datasheet HTML 67Page - Freescale Semiconductor, Inc Next Button
Zoom Inzoom in Zoom Outzoom out
 63 / 76 page
background image
MPC8306 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0
Freescale Semiconductor
63
Clocking
coherent system bus clock (csb_clk). Table 56 shows the expected frequency values for the CSB frequency
for selected csb_clk to SYS_CLK_IN ratios.
22.3
Core PLL Configuration
RCWL[COREPLL] selects the ratio between the internal coherent system bus clock (csb_clk) and the e300
core clock (core_clk). Table 57 shows the encodings for RCWL[COREPLL]. COREPLL values not listed
in Table 57 should be considered reserved.
Table 55. System PLL Multiplication Factors
RCWL[SPMF]
System PLL Multiplication Factor
0000
Reserved
0001
Reserved
0010
× 2
0011
× 3
0100
× 4
0101
× 5
0110
× 6
0111–1111
Reserved
Table 56. CSB Frequency Options
SPMF
csb_clk : sys_clk_in Ratio
SYS_CLK_IN(MHz)
25
33.33
66.67
csb_clk Frequency (MHz)
0010
2:1
133
0011
3:1
0100
4:1
133
0101
5:1
125
0110
6:1
Table 57. e300 Core PLL Configuration
RCWL[COREPLL]
core_clk : csb_clk Ratio
VCO Divider
0-1
2-5
6
nn
0000
n
PLL bypassed
(PLL off, csb_clk clocks core directly)
PLL bypassed
(PLL off, csb_clk clocks core directly)
00
0001
0
1:1
2
01
0001
0
1:1
4



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76


датащи скачать

Go To PDF Page


ссылки URL



Вашему бизинису помогли Аллдатащит?  [ DONATE ] 

Что такое Аллдатащит   |   реклама   |   контакт   |   Конфиденциальность   |   Ссылка на техническое описание    |   обмен ссыками   |   поиск по производителю
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com