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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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MPC8306EC датащи(PDF) 31 Page - Freescale Semiconductor, Inc |
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MPC8306EC датащи(HTML) 31 Page - Freescale Semiconductor, Inc |
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31 / 76 page  MPC8306 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0 Freescale Semiconductor 31 TDM/SI 9.2 TDM/SI AC Timing Specifications Table 29 provides the TDM/SI input and output AC timing specifications. Figure 20 provides the AC test load for the TDM/SI. Figure 20. TDM/SI AC Test Load Table 29. TDM/SI AC Timing Specifications1 Characteristic Symbol2 Min Max Unit TDM/SI outputs—External clock delay tSEKHOV 214 ns TDM/SI outputs—External clock High Impedance tSEKHOX 210 ns TDM/SI inputs—External clock input setup time tSEIVKH 5— ns TDM/SI inputs—External clock input hold time tSEIXKH 2— ns Notes: 1. Output specifications are measured from the 50% level of the rising edge of QE_CLK_IN to the 50% level of the signal. Timings are measured at the pin. 2. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tSEKHOX symbolizes the TDM/SI outputs external timing (SE) for the time tTDM/SI memory clock reference (K) goes from the high state (H) until outputs (O) are invalid (X). Output Z0 = 50 OVDD/2 RL = 50 |
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