MPC8306EC datasheet(25/76 Pages) FREESCALE

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MPC8306 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0

Freescale Semiconductor

Ethernet and MII Management

Figure 13 shows the MII receive AC timing diagram.

Figure 13. MII Receive AC Timing Diagram

8.2.2

RMII AC Timing Specifications

This section describes the RMII transmit and receive AC timing specifications.

8.2.2.1

RMII Transmit AC Timing Specifications

Table 20 provides the RMII transmit AC timing specifications.

Figure 14 provides the AC test load.

Figure 14. AC Test Load

Table 22. RMII Transmit AC Timing Specifications

At recommended operating conditions with OVDD of 3.3 V ± 300mV.

Parameter/Condition

Symbol1

Min

Typical

Max

Unit

REF_CLK clock

tRMX

—20—

REF_CLK duty cycle

tRMXH/tRMX

—

REF_CLK to RMII data TXD[1:0], TX_EN delay

tRMTKHDX

—

REF_CLK data clock rise VIL(min) to VIH(max)

tRMXR

1.0

—

4.0

REF_CLK data clock fall VIH(max) to VIL(min)

tRMXF

1.0

—

4.0

Note:

1. The symbols used for timing specifications follow the pattern of t(first three letters of functional block)(signal)(state)(reference)(state) for

inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tRMTKHDX symbolizes RMII

transmit timing (RMT) for the time tRMX clock reference (K) going high (H) until data outputs (D) are invalid (X). Note that, in

general, the clock reference symbol representation is based on two to three letters representing the clock of a particular

functional. For example, the subscript of tRMX represents the RMII(RM) reference (X) clock. For rise and fall times, the latter

convention is used with the appropriate letter: R (rise) or F (fall).

RX_CLK

RXD[3:0]

tMRDXKH

tMRX

tMRXH

tMRXR

tMRXF

RX_DV

RX_ER

tMRDVKH

Valid Data

Output

Z0 = 50 

OVDD/2

RL = 50 

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