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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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MPC8306EC датащи(PDF) 65 Page - Freescale Semiconductor, Inc |
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MPC8306EC датащи(HTML) 65 Page - Freescale Semiconductor, Inc |
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65 / 76 page  MPC8306 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0 Freescale Semiconductor 65 Clocking The RCWL[CEVCOD] denotes the QUICC Engine PLL VCO internal frequency as shown in Table 59. NOTE The VCO divider (RCWL[CEVCOD]) must be set properly so that the QUICC Engine VCO frequency is in the range of 300–600 MHz. The QUICC Engine frequency is not restricted by the CSB and core frequencies. The CSB, core, and QUICC Engine frequencies should be selected according to the performance requirements. The QUICC Engine VCO frequency is derived from the following equations: qe_clk = (primary clock input × CEPMF) (1 + CEPDF) QUICC Engine VCO Frequency = qe_clk × VCO divider × (1 + CEPDF) 22.5 Suggested PLL Configurations To simplify the PLL configurations, the MPC8306 might be separated into two clock domains. The first domain contains the CSB PLL and the core PLL. The core PLL is connected serially to the CSB PLL, and has the csb_clk as its input clock. The second clock domain has the QUICC Engine PLL. The clock domains are independent, and each of their PLLs are configured separately. Table 60 shows suggested PLL configurations for 33, 25, and 66 MHz input clocks. 00101 0 5 00110 0 6 00111 0 7 01000 0 8 01001–11111 0 Reserved Table 59. QUICC Engine PLL VCO Divider RCWL[CEVCOD] VCO Divider 00 2 01 4 10 8 11 Reserved Table 58. QUICC Engine PLL Multiplication Factors (continued) RCWL[CEPMF] RCWL[CEPDF] QUICC Engine PLL Multiplication Factor = RCWL[CEPMF]/ (1 + RCWL[CEPDF) |
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