352 datasheet(30/95 Pages) INTEL

30 / 95 page

Electrical Specifications

Datasheet

2.7.2

FSB Frequency Select Signals (BSEL[2:0])

The BSEL[2:0] signals are used to select the frequency of the processor input clock

(BCLK[1:0]). Table 18 defines the possible combinations of the signals and the

frequency associated with each combination. The required frequency is determined by

the processor, chipset, and clock synthesizer. All agents must operate at the same

frequency.

The Celeron D processor will operate at an 533 MHz FSB frequency (selected by a

133 MHz BCLK[1:0] frequency).

For more information about these signals, refer to Section 4.2.

2.7.3

Phase Lock Loop (PLL) and Filter

VCCA and VCCIOPLL are power sources required by the PLL clock generators for the

Celeron D processor silicon. Since these PLLs are analog in nature, they require low

noise power supplies for minimum jitter. Jitter is detrimental to the system: it degrades

external I/O timings as well as internal core timings (i.e., maximum frequency). To

prevent this degradation, these supplies must be low pass filtered from VTT.

The AC low-pass requirements, with input at VTT are as follows:

• < 0.2 dB gain in pass band

• < 0.5 dB attenuation in pass band < 1 Hz

• > 34 dB attenuation from 1 MHz to 66 MHz

• > 28 dB attenuation from 66 MHz to core frequency

The filter requirements are illustrated in Figure 3.

Table 18.

BSEL[2:0] Frequency Table for BCLK[1:0]

BSEL2

BSEL1

BSEL0

FSB Frequency

RESERVED

133 MHz

RESERVED

352 датащи(PDF) 30 Page - Intel Corporation