352 datasheet(24/95 Pages) INTEL

24 / 95 page

Electrical Specifications

Datasheet

NOTES:

Refer to Section 4.2 for signal descriptions.

The value of these signals during the active-to-inactive edge of RESET# defines the

processor configuration options. See Section 6.1 for details.

In processor systems where no debug port is implemented on the system board, these

signals are used to support a debug port interposer. In systems with the debug port

implemented on the system board, these signals are no connects.

TAP Output

Synchronous to

TCK

TDO

FSB Clock

Clock

BCLK[1:0], ITP_CLK[1:0]3

Power/Other

VCC, VTT, VCCA, VCCIOPLL, VID[5:0], VSS, VSSA,

GTLREF[1:0], COMP[5:4,1:0], RESERVED, TESTHI[13:0],

THERMDA, THERMDC, VCC_SENSE,

VCC_MB_REGULATION, VSS_SENSE,

VSS_MB_REGULATION, BSEL[2:0], SKTOCC#, DBR#3,

VTTPWRGD, BOOTSELECT, VTT_OUT_LEFT,

VTT_OUT_RIGHT, VTT_SEL, LL_ID[1:0], MSID[1:0], FCx,

IMPSEL

Table 7.

FSB Signal Groups (Sheet 2 of 2)

Signal Group

Type

Signals1

Table 8.

Signal Characteristics

Signals with RTT

Signals with No RTT

A[35:3]#, ADS#, ADSTB[1:0]#, AP[1:0]#,

BINIT#, BNR#, BOOTSELECT1, BPRI#,

D[63:0]#, DBI[3:0]#, DBSY#, DEFER#,

DP[3:0]#, DRDY#, DSTBN[3:0]#,

DSTBP[3:0]#, HIT#, HITM#, LOCK#, MCERR#,

MSID[1:0]1, PROCHOT#, REQ[4:0]#, RS[2:0]#,

RSP#, TRDY#, IMPSEL2

NOTES:

1. These signals have a 500–5000 Ω pull-up to VTT rather than on-die termination.

A20M#, BCLK[1:0], BPM[5:0]#, BSEL[2:0],

COMP[5:4,1:0], FERR#/PBE#, IERR#,

IGNNE#, INIT#, ITP_CLK[1:0], LINT0/INTR,

LINT1/NMI, PWRGOOD, RESET#, SKTOCC#,

SMI#, STPCLK#, TDO, TESTHI[13:0],

THERMDA, THERMDC, THERMTRIP#,

VID[5:0], VTTPWRGD, GTLREF[1:0], TCK,

TDI, TMS, TRST#, VTT_SEL

Open Drain Signals2

Signals that do not have RTT, nor are actively driven to their high-voltage level.

THERMTRIP#, FERR#/PBE#, IERR#, BPM[5:0]#,

BR0#, TDO, LL_ID[1:0], FCx

Table 9.

Signal Reference Voltages

GTLREF

VTT/2

BPM[5:0]#, LINT0/INTR, LINT1/NMI, RESET#,

BINIT#, BNR#, HIT#, HITM#, MCERR#, PROCHOT#,

BR0#, A[35:0]#, ADS#, ADSTB[1:0]#, AP[1:0]#,

BPRI#, D[63:0]#, DBI[3:0]#, DBSY#, DEFER#,

DP[3:0]#, DRDY#, DSTBN[3:0]#, DSTBP[3:0]#,

LOCK#, REQ[4:0]#, RS[2:0]#, RSP#, TRDY#

BOOTSELECT, VTTPWRGD, A20M#,

IGNNE#, INIT#, MSID[1:0],

PWRGOOD1, SMI#, STPCLK#, TCK1,

TDI1, TMS1, TRST#1

NOTES:

These signals also have hysteresis added to the reference voltage. See Table 12 for more

information.

352 датащи(PDF) 24 Page - Intel Corporation

352 датащи(HTML) 24 Page - Intel Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95

датащи скачать

ссылки URL