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Land Listing and Signal Descriptions

Datasheet

FERR#/PBE#

Output

FERR#/PBE# (floating point error/pending break event) is a

multiplexed signal and its meaning is qualified by STPCLK#. When

STPCLK# is not asserted, FERR#/PBE# indicates a floating-point

error and will be asserted when the processor detects an unmasked

floating-point error. When STPCLK# is not asserted, FERR#/PBE# is

similar to the ERROR# signal on the Intel 387 coprocessor, and is

included for compatibility with systems using MS-DOS*-type

floating-point error reporting. When STPCLK# is asserted, an

assertion of FERR#/PBE# indicates that the processor has a pending

break event waiting for service. The assertion of FERR#/PBE#

indicates that the processor should be returned to the Normal state.

For additional information on the pending break event functionality,

including the identification of support of the feature and enable/

disable information, refer to volume 3 of the Intel Architecture

Software Developer's Manual and the Intel Processor Identification

and the CPUID Instruction application note.

GTLREF[1:0]

Input

GTLREF[1:0] determine the signal reference level for GTL+ input

signals. GTLREF is used by the GTL+ receivers to determine if a

signal is a logical 0 or logical 1.

HIT#

HITM#

Input/

Output

Input/

Output

HIT# (Snoop Hit) and HITM# (Hit Modified) convey transaction

snoop operation results. Any FSB agent may assert both HIT# and

HITM# together to indicate that it requires a snoop stall, which can

be continued by reasserting HIT# and HITM# together.

IERR#

Output

IERR# (Internal Error) is asserted by a processor as the result of an

internal error. Assertion of IERR# is usually accompanied by a

SHUTDOWN transaction on the processor FSB. This transaction may

optionally be converted to an external error signal (e.g., NMI) by

system core logic. The processor will keep IERR# asserted until the

assertion of RESET#.

This signal does not have on-die termination. Refer to Section 2.5.2

for termination requirements.

IGNNE#

Input

IGNNE# (Ignore Numeric Error) is asserted to the processor to

ignore a numeric error and continue to execute noncontrol floating-

point instructions. If IGNNE# is de-asserted, the processor

generates an exception on a noncontrol floating-point instruction if a

previous floating-point instruction caused an error. IGNNE# has no

effect when the NE bit in control register 0 (CR0) is set.

IGNNE# is an asynchronous signal. However, to ensure recognition

of this signal following an Input/Output write instruction, it must be

valid along with the TRDY# assertion of the corresponding Input/

Output Write bus transaction.

IMPSEL

Input

IMPSEL input will determine whether the processor uses a 50 Ω or

60 Ω buffer. This pin/land must be tied to GND on 50 Ω platforms

and left as NC on 60 Ω platforms. This input has a weak internal

pull-up to VTT.

Table 25.

Signal Description (Sheet 1 of 9)

Name

Type

Description

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