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Electrical Specifications

Datasheet

2.2.2

VTT Decoupling

Decoupling must be provided on the motherboard. Decoupling solutions must be sized

to meet the expected load. To insure compliance with the specifications, various factors

associated with the power delivery solution must be considered including regulator

type, power plane and trace sizing, and component placement. A conservative

decoupling solution would consist of a combination of low ESR bulk capacitors and high

frequency ceramic capacitors.

2.2.3

FSB Decoupling

The processor integrates signal termination on the die. In addition, some of the high

frequency capacitance required for the FSB is included on the processor package.

However, additional high frequency capacitance must be added to the motherboard to

properly decouple the return currents from the front side bus. Bulk decoupling must

also be provided by the motherboard for proper [A]GTL+ bus operation.

2.3

Voltage Identification

The Voltage Identification (VID) specification for the processor is defined by the Voltage

Regulator-Down (VRD) 10.1 Design Guide For Desktop and Transportable LGA775

Socket. The voltage set by the VID signals is the reference VR output voltage to be

delivered to the processor VCC lands (see Section 2.5.3 for VCC overshoot

specifications). Refer to Table 14 for the DC specifications for these signals. A minimum

voltage for each processor frequency is provided in Table 4.

Individual processor VID values may be calibrated during manufacturing such that two

devices at the same core speed may have different default VID settings. This is

reflected by the VID Range values provided in Table 4. Refer to the Intel® Celeron® D

Processor 300 Sequence Specification Update for further details on specific valid core

frequency and VID values of the processor.

The processor uses 6 voltage identification signals, VID[5:0], to support automatic

selection of power supply voltages. Table 2 specifies the voltage level corresponding to

the state of VID[5:0]. A ‘1’ in this table refers to a high voltage level and a ‘0’ refers to

a low voltage level. If the processor socket is empty (VID[5:0] = x11111), or the

voltage regulation circuit cannot supply the voltage that is requested, it must disable

itself. Refer to the Voltage Regulator-Down (VRD) 10.1 Design Guide For Desktop and

Transportable LGA775 Socket for further details.

The processor provides the ability to operate while transitioning to an adjacent VID and

its associated processor core voltage (VCC). This will represent a DC shift in the load

line. Note that a low-to-high or high-to-low voltage state change may result in as many

VID transitions as necessary to reach the target core voltage. Transitions above the

specified VID are not permitted. Table 4 includes VID step sizes and DC shift ranges.

Minimum and maximum voltages must be maintained as shown in Table 5 and Figure 1

as measured across the VCC_SENSE and VSS_SENSE lands.

The VRM or VRD used must be capable of regulating its output to the value defined by

the new VID. DC specifications for dynamic VID transitions are included in Table 4, and

Table 5. Refer to the Voltage Regulator-Down (VRD) 10.1 Design Guide For Desktop

and Transportable LGA775 Socket for further details.

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