DS26521 datasheet(63/258 Pages) MAXIM

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DS26521 Single T1/E1/J1 Transceiver

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8.10.1.1

HDLC FIFO Control

Control of the transmit and receive FIFOs is accomplished via the Receive HDLC FIFO Control (RHFC) and

Transmit HDLC FIFO Control (THFC) registers. The FIFO control registers set the watermarks for the FIFO.

When the receive FIFO fills above the high watermark, the RHWM bit (RRTS5.1) is set. RHWM and THRM are

real-time bits and remain set as long as the FIFO’s write pointer is above the watermark. When the transmit FIFO

empties below the low watermark, the TLWM bit in the TRTS2 register is set. TLWM is a real-time bit and remains

set as long as the transmit FIFO’s write pointer is below the watermark. If enabled, this condition can also cause an

interrupt via the

INTB pin.

If the receive HDLC FIFO does overrun, the current packet being processed is dropped. The receive FIFO is

emptied. The packet status bit in RRTS5 and RLS5.5 (ROVR) indicate an overrun.

8.10.1.2

Receive HDLC Packet Bytes Available

The lower 7 bits of the Receive HDLC Packet Bytes Available register (RHPBA) indicates the number of bytes (0 to

64) that can be read from the receive FIFO. The value indicated by this register informs the host as to how many

bytes can be read from the receive FIFO without going past the end of a message. This value refers to one of four

possibilities: the first part of a packet, the continuation of a packet, the last part of a packet, or a complete packet.

After reading the number of bytes indicated by this register, the host then checks the HDLC status registers for

detailed message status.

If the value in the RHPBA register refers to the beginning portion of a message or continuation of a message, then

the MSB of the RHPBA register returns a value of 1. This indicates that the host can safely read the number of

bytes returned by the lower 7 bits of the RHPBA register, but there is no need to check the information register

since the packet has not yet terminated (successfully or otherwise).

8.10.1.3

HDLC Status and Information

RRTS5, RLS5, and TLS2 provide status information for the HDLC controller. When a particular event has occurred

(or is occurring), the appropriate bit in one of these registers is set to 1. Some of the bits in these registers are

latched and some are real-time bits that are not latched. This section contains register descriptions that list which

bits are latched and which are real-time. With the latched bits, when an event occurs and a bit is set to 1, it remains

set until the user reads and clears that bit. The bit is cleared when a 1 is written to the bit, and it will not be set

again until the event has occurred again. The real-time bits report the current instantaneous conditions that are

occurring and the history of these bits is not latched.

Like the other latched status registers, the user follows a read of the status bit with a write. The byte written to the

writing to the status register). The user writes a byte to one of these registers, with a 1 in the bit positions he or she

wishes to clear and a 0 in the bit positions he or she does not wish to clear.

The HDLC status registers RLS5 and TLS2 have the ability to initiate a hardware interrupt via the

INTB output

signal. Each of the events in this register can be either masked or unmasked from the interrupt pin via the HDLC

interrupt mask registers RIM5 and TIM2. Interrupts force the

INTB signal low when the event occurs. The INTB pin

is allowed to return high (if no other interrupts are present) when the user reads the event bit that caused the

interrupt to occur.

8.10.1.4

HDLC Receive Example

The HDLC status registers in the DS26521 allow for flexible software interface to meet the user’s preferences.

When receiving HDLC messages, the host can choose to be interrupt driven, or to poll to desired status registers,

or a combination of polling and interrupt processes can be used. An example routine for using the DS26521 HDLC

receiver is given in Figure 8-15.

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