DS26521 datasheet(3/258 Pages) MAXIM

3 / 258 page

DS26521 Single T1/E1/J1 Transceiver

3 of 258

8.9.8

E1 Automatic Alarm Generation .......................................................................................................... 54

8.9.9

Error-Count Registers .......................................................................................................................... 55

8.9.10

DS0 Monitoring Function...................................................................................................................... 57

8.9.11

Transmit Per-Channel Idle Code Insertion........................................................................................... 58

8.9.12

Receive Per-Channel Idle Code Insertion............................................................................................ 58

8.9.13

Per-Channel Loopback ........................................................................................................................ 58

8.9.14

E1 G.706 Intermediate CRC-4 Updating (E1 Mode Only) ................................................................... 58

8.9.15

T1 Programmable In-Band Loop Code Generator............................................................................... 59

8.9.16

T1 Programmable In-Band Loop Code Detection................................................................................ 60

8.9.17

Framer Payload Loopbacks ................................................................................................................. 61

8.10

HDLC CONTROLLERS ................................................................................................................62

8.10.1

Receive HDLC Controller..................................................................................................................... 62

8.10.2

Transmit HDLC Controller.................................................................................................................... 65

8.11

LINE INTERFACE UNITS (LIUS) ....................................................................................................67

8.11.1

LIU Operation....................................................................................................................................... 69

8.11.2

Transmitter ........................................................................................................................................... 70

8.11.3

Receiver ............................................................................................................................................... 73

8.11.4

Jitter Attenuator.................................................................................................................................... 76

8.11.5

LIU Loopbacks ..................................................................................................................................... 77

8.12

BIT-ERROR-RATE TEST (BERT) FUNCTION ................................................................................79

8.12.1

BERT Repetitive Pattern Set ............................................................................................................... 80

8.12.2

BERT Error Counter............................................................................................................................. 80

DEVICE REGISTERS .....................................................................................................81

9.1

REGISTER LISTINGS ......................................................................................................................81

9.1.1

Global Register List.............................................................................................................................. 82

9.1.2

Framer Register List............................................................................................................................. 83

9.1.3

LIU and BERT Register List ................................................................................................................. 90

9.2

REGISTER BIT MAPS......................................................................................................................91

9.2.1

Global Register Bit Map ....................................................................................................................... 91

9.2.2

Framer Register Bit Map ...................................................................................................................... 92

9.2.3

LIU Register Bit Map .......................................................................................................................... 100

9.2.4

BERT Register Bit Map ...................................................................................................................... 100

9.3

GLOBAL REGISTER DEFINITIONS ..................................................................................................101

9.4

FRAMER REGISTER DEFINITIONS .................................................................................................109

9.4.1

Receive Register Definitions .............................................................................................................. 109

9.4.2

Transmit Register Definitions ............................................................................................................. 168

9.5

LIU REGISTER DEFINITIONS.........................................................................................................203

9.6

BERT REGISTER DEFINITIONS.....................................................................................................212

10.

FUNCTIONAL TIMING .................................................................................................220

10.1

T1 RECEIVER FUNCTIONAL TIMING DIAGRAMS ..........................................................................220

10.2

T1 TRANSMITTER FUNCTIONAL TIMING DIAGRAMS ....................................................................225

10.3

E1 RECEIVER FUNCTIONAL TIMING DIAGRAMS ..........................................................................230

10.4

E1 TRANSMITTER FUNCTIONAL TIMING DIAGRAMS ....................................................................232

11.

OPERATING PARAMETERS .......................................................................................235

11.1

THERMAL CHARACTERISTICS....................................................................................................236

11.2

LINE INTERFACE CHARACTERISTICS..........................................................................................236

12.

AC TIMING CHARACTERISTICS ................................................................................237

12.1

MICROPROCESSOR BUS AC CHARACTERISTICS........................................................................237

12.1.1

Parallel Port Mode.............................................................................................................................. 237

12.1.2

SPI Bus Mode .................................................................................................................................... 240

12.2

JTAG INTERFACE TIMING.........................................................................................................248

12.3

SYSTEM CLOCK AC CHARACTERISTICS ....................................................................................249

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