DS26521 datasheet(5/258 Pages) MAXIM

5 / 258 page

DS26521 Single T1/E1/J1 Transceiver

5 of 258

LIST OF FIGURES

Figure 6-1. Block Diagram ......................................................................................................................................... 17

Figure 6-2. Detailed Block Diagram........................................................................................................................... 18

Figure 8-1. SPI Serial Port Access for Read Mode (SPI_CPOL = 0, SPI_CPHA = 0).............................................. 26

Figure 8-2. SPI Serial Port Access for Read Mode (SPI_CPOL = 1, SPI_CPHA = 0).............................................. 26

Figure 8-3. SPI Serial Port Access for Read Mode (SPI_CPOL = 0, SPI_CPHA = 1).............................................. 26

Figure 8-4. SPI Serial Port Access for Read Mode (SPI_CPOL = 1, SPI_CPHA = 1).............................................. 26

Figure 8-5. SPI Serial Port Access for Write Mode (SPI_CPOL = 0, SPI_CPHA = 0) .............................................. 27

Figure 8-6. SPI Serial Port Access for Write Mode (SPI_CPOL = 1, SPI_CPHA = 0) .............................................. 27

Figure 8-7. SPI Serial Port Access for Write Mode (SPI_CPOL = 0, SPI_CPHA = 1) .............................................. 27

Figure 8-8. SPI Serial Port Access for Write Mode (SPI_CPOL = 1, SPI_CPHA = 1) .............................................. 27

Figure 8-9. Backplane Clock Generation................................................................................................................... 28

Figure 8-10. Device Interrupt Information Flow Diagram........................................................................................... 31

Figure 8-11. IBO Example Circuit .............................................................................................................................. 35

Figure 8-12. RSYNC Input in H.100 (CT Bus) Mode................................................................................................. 36

Figure 8-13. TSSYNCIO (Input Mode) Input in H.100 (CT Bus) Mode ..................................................................... 37

Figure 8-14. CRC-4 Recalculate Method .................................................................................................................. 58

Figure 8-15. Receive HDLC Example........................................................................................................................ 64

Figure 8-16. HDLC Message Transmit Example....................................................................................................... 66

Figure 8-17. Basic Balanced Network Connections .................................................................................................. 68

Figure 8-18. T1/J1 Transmit Pulse Templates .......................................................................................................... 71

Figure 8-19. E1 Transmit Pulse Templates ............................................................................................................... 72

Figure 8-20. Typical Monitor Application ................................................................................................................... 74

Figure 8-21. Jitter Attenuation ................................................................................................................................... 76

Figure 8-22. Analog Loopback................................................................................................................................... 77

Figure 8-23. Local Loopback ..................................................................................................................................... 77

Figure 8-24. Remote Loopback ................................................................................................................................. 78

Figure 8-25. Dual Loopback ...................................................................................................................................... 78

Figure 10-1. T1 Receive-Side D4 Timing ................................................................................................................ 220

Figure 10-2. T1 Receive-Side ESF Timing.............................................................................................................. 220

Figure 10-3. T1 Receive-Side Boundary Timing (Elastic Store Disabled)............................................................... 221

Figure 10-4. T1 Receive-Side 1.544MHz Boundary Timing (Elastic Store Enabled).............................................. 221

Figure 10-5. T1 Receive-Side 2.048MHz Boundary Timing (Elastic Store Enabled).............................................. 222

Figure 10-6. T1 Receive-Side Interleave Bus Operation—BYTE Mode.................................................................. 223

Figure 10-7. T1 Receive-Side Interleave Bus Operation—FRAME Mode .............................................................. 224

Figure 10-8. T1 Transmit-Side D4 Timing ............................................................................................................... 225

Figure 10-9. T1 Transmit-Side ESF Timing ............................................................................................................. 225

Figure 10-10. T1 Transmit-Side Boundary Timing (Elastic Store Disabled)............................................................ 226

Figure 10-11. T1 Transmit-Side 1.544MHz Boundary Timing (Elastic Store Enabled)........................................... 226

Figure 10-12. T1 Transmit-Side 2.048MHz Boundary Timing (Elastic Store Enabled)........................................... 227

Figure 10-13. T1 Transmit-Side Interleave Bus Operation—BYTE Mode............................................................... 228

Figure 10-14. T1 Transmit Interleave Bus Operation—FRAME Mode.................................................................... 229

Figure 10-15. E1 Receive-Side Timing.................................................................................................................... 230

Figure 10-16. E1 Receive-Side Boundary Timing (Elastic Store Disabled) ............................................................ 230

Figure 10-17. E1 Receive-Side 1.544MHz Boundary Timing (Elastic Store Enabled)............................................ 231

Figure 10-18. E1 Receive-Side 2.048MHz Boundary Timing (Elastic Store Enabled)............................................ 231

Figure 10-19. E1 Transmit-Side Timing................................................................................................................... 232

Figure 10-20. E1 Transmit-Side Boundary Timing (Elastic Store Disabled) ........................................................... 232

Figure 10-21. E1 Transmit-Side 1.544MHz Boundary Timing (Elastic Store Enabled)........................................... 233

Figure 10-22. E1 Transmit-Side 2.048MHz Boundary Timing (Elastic Store Enabled)........................................... 233

Figure 10-23. E1 G.802 Timing ............................................................................................................................... 234

Figure 12-1. Intel Bus Read Timing (BTS = 0) ........................................................................................................ 238

Figure 12-2. Intel Bus Write Timing (BTS = 0)......................................................................................................... 238

Figure 12-3. Motorola Bus Read Timing (BTS = 1) ................................................................................................. 239

Figure 12-4. Motorola Bus Write Timing (BTS = 1) ................................................................................................. 239

Figure 12-5. SPI Interface Timing Diagram ............................................................................................................. 241

Figure 12-6. Receive Framer Timing—Backplane (T1 Mode)................................................................................. 243

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