DS26521 datasheet(46/258 Pages) MAXIM

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DS26521 Single T1/E1/J1 Transceiver

46 of 258

8.9.4.3 Receive-Signaling Operation

There are two methods to access receive-signaling data and provide transmit-signaling data: processor based (i.e.,

software based) or hardware based. Processor based refers to access through the transmit- and receive-signaling

registers, RS1:RS16. Hardware based refers to the RSIG pin. Both methods can be used simultaneously.

8.9.4.3.1 Processor-Based Signaling

Signaling information is sampled from the receive data stream and copied into the receive-signaling registers,

RS1:RS16. The signaling information in these registers is always updated on multiframe boundaries. This function

is always enabled.

8.9.4.3.2 Change of State

To avoid constant monitoring of the receive-signaling registers, the DS26521 can be programmed to alert the host

when any specific channel or channels undergo a change of their signaling state. RSCSE1:RSCSE4 are used to

select which channels can cause a change-of-state indication. The change of state is indicated in Latched Status

multiframes before a change-of-state indication is indicated. The user can enable the

INTB pin to toggle low upon

detection of a change in signaling by setting the interrupt mask bit RIM4.3. The signaling integration mode is global

and cannot be enabled on a channel-by-channel basis.

The user can identity which channels have undergone a signaling change of state by reading the receive-signaling

status (RSS1:RSS4) registers. The information from these registers tells the user which RSx register to read for the

new signaling data. All changes are indicated in the RSS1:RSS4 registers regardless of the RSCSE1:RSCSE4

registers.

8.9.4.3.3 Hardware-Based Receive Signaling

In hardware-based signaling, the signaling data can be obtained from the RSER pin or the RSIG pin. RSIG is a

signaling PCM stream output on a channel-by-channel basis from the signaling buffer. The T1 robbed bit or E1

TS16 signaling data is still present in the original data stream at RSER. The signaling buffer provides signaling data

to the RSIG pin and also allows signaling data to be reinserted into the original data stream in a different alignment

that is determined by a multiframe signal from the RSYNC pin. In this mode, the receive elastic store can be

enabled or disabled. If the receive elastic store is enabled, the backplane clock (RSYSCLK) can be either

1.544MHz or 2.048MHz. In the ESF framing mode, the ABCD signaling bits are output on RSIG in the lower nibble

of each channel. The RSIG data is updated once a multiframe (3ms for T1 ESF, 1.5ms for T1 D4, 2ms for E1 CAS)

unless a signaling freeze is in effect. In the D4 framing mode, the AB signaling bits are output twice on RSIG in the

lower nibble of each channel. Thus, bits 5 and 6 contain the same data as bits 7 and 8, respectively, in each

channel.

8.9.4.3.4 Receive-Signaling Reinsertion at RSER

In this mode, the user provides a multiframe sync at the RSYNC pin and the signaling data will be reinserted based

on this alignment. In T1 mode, this results in two copies of the signaling data in the RSER data stream. The original

signaling data is based on the Fs/ESF frame positions, and the realigned data is based on the user-supplied

multiframe sync applied at RSYNC. In voice channels, this extra copy of signaling data is of little consequence.

Reinsertion can be avoided in data channels since this feature is activated on a per-channel basis. For reinsertion,

the elastic store must be enabled; for T1, the backplane clock can be either 1.544MHz or 2.048MHz. E1 signaling

information cannot be reinserted into a 1.544MHz backplane.

Signaling-reinsertion mode is enabled on a per-channel basis by setting the receive-signaling reinsertion channel

select bit high in the Receive-Signaling Reinsertion Enable register (RSI1:RSI4). The channels that are to have

signaling reinserted are selected by writing to the RSI1:RSI4 registers. In E1 mode, the user generally selects all

channels or none for reinsertion.

8.9.4.3.5 Force Receive-Signaling All Ones

In T1 mode, the user can, on a per-channel basis, force the robbed-bit signaling bit positions to 1. This is done by

using the T1-mode Receive-Signaling All-Ones Insertion registers (T1RSAOI1:T1RSAOI3). The user sets the

channel select bit in the T1RSAOI1:T1RSAOI3 registers to select the channels that are to have the signaling forced

to one.

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