DS26521 datasheet(2/258 Pages) MAXIM

2 / 258 page

DS26521 Single T1/E1/J1 Transceiver

2 of 258

TABLE OF CONTENTS

DETAILED DESCRIPTION ...............................................................................................9

1.1

MAJOR OPERATING MODES .............................................................................................................9

FEATURE HIGHLIGHTS ................................................................................................10

2.1

GENERAL ......................................................................................................................................10

2.2

LINE INTERFACE ............................................................................................................................10

2.3

CLOCK SYNTHESIZER ....................................................................................................................10

2.4

JITTER ATTENUATOR .....................................................................................................................10

2.5

FRAMER/FORMATTER ....................................................................................................................10

2.6

SYSTEM INTERFACE ......................................................................................................................11

2.7

HDLC CONTROLLERS ...................................................................................................................12

2.8

TEST AND DIAGNOSTICS ................................................................................................................12

2.9

MICROCONTROLLER PARALLEL PORT.............................................................................................12

2.10

SLAVE SERIAL PERIPHERAL INTERFACE (SPI) FEATURES ............................................................12

APPLICATIONS..............................................................................................................13

SPECIFICATIONS COMPLIANCE .................................................................................14

ACRONYMS AND GLOSSARY......................................................................................16

BLOCK DIAGRAMS .......................................................................................................17

PIN DESCRIPTIONS ......................................................................................................19

7.1

PIN FUNCTIONAL DESCRIPTION......................................................................................................19

FUNCTIONAL DESCRIPTION........................................................................................25

8.1

MICROPROCESSOR INTERFACE......................................................................................................25

8.1.1

Parallel Port Mode................................................................................................................................ 25

8.1.2

SPI Serial Port Mode............................................................................................................................ 25

8.1.3

SPI Functional Timing Diagrams ......................................................................................................... 25

8.2

CLOCK STRUCTURE.......................................................................................................................28

8.2.1

Backplane Clock Generation ............................................................................................................... 28

8.3

RESETS AND POWER-DOWN MODES..............................................................................................29

8.4

INITIALIZATION AND CONFIGURATION..............................................................................................30

8.4.1

Example Device Initialization Sequence .............................................................................................. 30

8.5

GLOBAL RESOURCES ....................................................................................................................30

8.6

PORT RESOURCES ........................................................................................................................30

8.7

DEVICE INTERRUPTS .....................................................................................................................30

8.8

SYSTEM BACKPLANE INTERFACE ...................................................................................................32

8.8.1

Elastic Stores ....................................................................................................................................... 32

8.8.2

IBO Multiplexer..................................................................................................................................... 35

8.8.3

H.100 (CT Bus) Compatibility .............................................................................................................. 36

8.8.4

Receive and Transmit Channel Blocking Registers............................................................................. 37

8.8.5

Transmit Fractional Support (Gapped Clock Mode) ............................................................................ 37

8.8.6

Receive Fractional Support (Gapped Clock Mode) ............................................................................. 37

8.9

FRAMERS......................................................................................................................................38

8.9.1

T1 Framing........................................................................................................................................... 38

8.9.2

E1 Framing........................................................................................................................................... 41

8.9.3

T1 Transmit Synchronizer .................................................................................................................... 43

8.9.4

Signaling .............................................................................................................................................. 44

8.9.5

T1 Data Link......................................................................................................................................... 48

8.9.6

E1 Data Link......................................................................................................................................... 50

8.9.7

Maintenance and Alarms ..................................................................................................................... 51

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